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參數(shù)資料
| 型號： | AM79C974 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | PCnetTM -的SCSI結(jié)合以太網(wǎng)和SCSI控制器PCI系統(tǒng) |
| 文件頁數(shù)： | 120/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974 |
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120
Am79C974
Recommendation for Power and Ground
Decoupling
APPENDIX C
The PCnet-SCSI controller is an integrated, combina-
tion Ethernet and Fast SCSI controller, which contains
both digital and analog circuitry. The analog circuitry
contains a high speed Phase-Locked Loop (PLL) and
Voltage Controlled Oscillator (VCO). Because of the
mixed signal characteristics of this chip, some extra pre-
cautions must be taken into account when designing
with this device.
Digital Decoupling
The PCnet-SCSI controller separates the digital power
supply pins into two groups. The V
SSB
and V
DDB
pins sup-
ply power to the I/O buffers that connect to the PCI bus.
The V
SS
and V
DD
pins supply power to all internal cir-
cuitry. AMD recommends that at least one low fre-
quency bulk decoupling capacitor be used for each
group of digital power pins. 22
μ
F capacitors have
worked well for this. In addition, a total of four or five
0.1
μ
F capacitors have proven sufficient around V
SSB
and V
DDB
pins that supply the drives of the PCI bus out-
put pins. An additional two to the three 0.1
μ
F capacitors
shoud be used around the V
SS
and V
DD
pins.
The CMOS technology used in fabricating the PCnet-
SCSI controller employs an n-type substrate. In this
technology, all V
DD
and V
DDB
pins are electrically con-
nected to each other internally. Hence, in a multi-layer
board, when decoupling between V
DD
/V
DDB
and critical
V
SS
/V
SSB
pins, the specific V
DD
/V
DDB
pin that you connect
to is not critical. In fact, the V
DD
/V
DDB
connection of the
decoupling capacitor can be made directly to the power
plane, near the closest V
DD
/V
DDB
pin to the V
SS
/V
SSB
pin
of interest. However, we recommend that the V
SS
/V
SSB
connection of the decoupling capacitor be made directly
to the V
SS
/V
SSB
pin of interest as shown.
V
DD
/V
DDB
Pin
V
SS
/V
SSB
Pin
PCnet-SCSI
via to V
DD
plane
via to V
SS
plane
18681A-61
AMD recommends that at least one low-frequency bulk
decoupling capacitor be used in the area of the PCnet-
SCSI controller. 22
μ
F capacitors have worked well for
this. In addition, a total of four or five 0.1
μ
F capacitors
have proven sufficient around the V
SSB
and V
DDB
pins
that supply the drivers of the PCI bus output pins.
Analog Decoupling
The most critical pins are the analog supply and ground
pins. All of the analog supply and ground pins are lo-
cated in one corner of the device. Specific requirements
of the analog supply pins are listed below.
AV
SS1
(Pin 100) and AV
DD3
(Pin 96)
These pins provide the power and ground for the
Twisted Pair and AUI drivers. Hence, they are very
noisy. A dedicated 0.1
μ
F capacitor between these pins
is recommended.
AV
SS2
(Pin 98) and AV
DD2
(Pin 108)
These pins are the most critical pins on the PCnet-SCSI
controller because they provide the power and ground
for the PLL portion of the chip. The VCO portion of the
PLL is sensitive to noise in the 60 kHz –200 kHz. range.
To prevent noise in this frequency range from disrupting
the VCO, AMD strongly recommends that the low-pass
filter shown below be implemented on these pins. Tests
using this filter have shown significantly increased noise
immunity and reduced Bit Error Rate (BER) statistics in
designs using the PCnet-SCSI controller.
PCnet-SCSI
AV
DD
Pin 108
AV
SS
Pin 98
V
DD
Plane
33
μ
F to 6.8
μ
F
R1
2.7
to 20
18681A-62
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