參數(shù)資料
型號: AM79C974
廠商: Advanced Micro Devices, Inc.
英文描述: PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
中文描述: PCnetTM -的SCSI結合以太網(wǎng)和SCSI控制器PCI系統(tǒng)
文件頁數(shù): 80/153頁
文件大?。?/td> 838K
代理商: AM79C974
AMD
P R E L I M I N A R Y
80
Am79C974
When WAC (bits 11:0) again reaches the next 4K byte
boundary, the next MDL entry is read into the WAC. The
operation continues in this way until WMAC register
reaches the last MDL entry (Page Frame Address #n in
this example).
4. The WAC register points to the beginning of the last
page and the DMA operation continues until the
byte count is exhausted in the Working Byte
Counter (WBC) register. When WBC=0, the chip
stops incrementing the WAC register. This is
shown below.
18681A/1-34
0
12
31
WAC
4K Page #n
Page Frame Address #n
From the MDL
WBC = 0
0
Data
DMA Scatter-Gather Operation
(Non-4k aligned elements MDL not set)
There is another way to implement a scatter-gather op-
eration which does not force the data elements to be
aligned on 4k boundaries. It assumes a “traditional”
scatter-gather list of the following format:
Element 0
Physical Address Byte Count
Element 1
Physical Address Byte Count
...
Element n
Physical Address Byte Count
This second implementation is described as follows:
1. Set the SCSI Start Transfer Count Register
((B)+00h, (B)+04h, (B)+38h) to the Byte count of
the first Scatter-Gather element.
2. Program the DMA Starting Transfer Count Regis-
ter ((B)+44h) to the Byte Count of the first Scatter-
Gather element.
3. Program the DMA Starting Physical Address Reg-
ister ((B)+48h) to the Physical Address of the first
Scatter-Gather element.
4. Start the SCSI operation by issuing a SCSI Infor-
mation Transfer command.
5. Start the DMA Engine with DMA Transfer Interrupt
Enable (Bit 6, (B)+40h).
6. When the Scatter-Gather element’s Byte Count
is exhausted, the DMA engine will generate an
interrupt.
7. Reprogram the next Scatter-Gather element’s Byte
Count into the SCSI Start Transfer Count Register
and the DMA Starting Transfer Count Register.
8. Reprogram the DMA Starting Physical Address
Register ((B)+48h) to the Physical Address of the
next Scatter-Gather element.
9. Repeat steps 4–8 until the Scatter-Gather list is
completed.
Interrupts
Interrupts may come from two sources: the DMA engine
or the SCSI block. Upon receipt of an interrupt
(INTA
as-
serted), the DMA Status register should be serviced first
to identify the interrupt source(s). DMA engine related
interrupts are cleared when the related flags are read in
the DMA Status register. However, SCSI block inter-
rupts will be cleared only when the SCSI Status, Internal
State, and Interrupt Status Registers are read.
Interrupts are caused by:
Successful completion of a DMA transfer request.
(Bit 6 in the DMA Command Register ((B+40h)
must be set to enable this interrupt)
An address error occurred on the PCI bus during a
DMA transfer (Bit 6 in the DMA Command Regis-
ter ((B)+40h) must be set to enable this interrupt)
The PWDN pin is first asserted
After completion of each page transfer during MDL
operations. (Bit 5 in the DMA Command Register
((B)+40h) must be set to enable this interrupt)
An interrupt from the SCSI block will automatically set
bit 4 (SCSIINT) in the DMA Status register (Address
(B)+54h). The SCSI block will generate an interrupt un-
der the following conditions:
SCSI Reset occurred
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相關代理商/技術參數(shù)
參數(shù)描述
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