參數(shù)資料
型號： AM79C974
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
中文描述： PCnetTM -的SCSI結(jié)合以太網(wǎng)和SCSI控制器PCI系統(tǒng)
文件頁數(shù)： 82/153頁
文件大小： 838K
代理商： AM79C974
AMD
P R E L I M I N A R Y
82
Am79C974
When this feature is enabled, the Am79C974 will check
parity on all data received from the SCSI bus. Any de-
tected error will be flagged by setting bit 5 in the SCSI
Status Register, and
ATN
will be asserted on the SCSI
bus. However, no interrupt will be generated.
When this feature is disabled (bit 4 set to ‘0’), no parity
check is done on incoming bytes. Note that the parity on
the PCI bus is generated internally and is distinct from
the parity received from the SCSI bus.
Parity Generating on the SCSI Bus
For each byte transferred to the SCSI bus, parity gen-
eration is done automatically.
Reset Levels
The Am79C794 has two reset pins and two reset com-
mands that affect the SCSI block. The
RST
pin resets
the whole chip including the SCSI controller, the Ether-
net controller, and the PCI interface.
The Reset Device command causes almost the same
effect on the SCSI controller that the
RST
pin does.
However, the Reset Device command has no effect on
the Ethernet controller or the PCI interface. Also, after
the Reset Device command has been issued, the user
must issue a NOP command before another command
can be executed.
The action of the
RST
signal or the Reset Device com-
mand is called Hard Reset.
The
SCSI^RST
pin is a bidirectional signal on the SCSI
bus that resets a portion of the SCSI logic when it is as-
serted by a device on the SCSI bus. Similarly the
Am79C794 can assert the
SCSI^RST
signal to cause all
of the other devices on the SCSI bus to reset.
The Reset SCSI command causes the same effect on
the SCSI controller that the
SCSI^RST
pin does, except
that this command also causes the
SCSI^RST
pin to be
asserted so that all other (external) devices on the SCSI
bus are also reset. Once a SCSI Reset command has
been executed, the
SCSI^RST
signal will remain as-
serted until a Hard Reset has occurred.
The action of the
SCSI^RST
signal and the Reset SCSI
command is called Soft Reset.
In addition there is a third type of reset, called Discon-
nected Reset, that is caused by certain sequences on
the SCSI bus. These three types of reset are described
in the following sections.
Hard Resets: (H)
This reset occurs at power up, when the
RST
pin is as-
serted through external hardware, or when the Reset
Device command is issued by writing 02h to the SCSI
command register at ((B)+0Ch). Hard reset causes all
chip functions to halt and resets all internal state ma-
chines. It leaves the SCSI block in the disconnected
state. It leaves all SCSI registers in their default states.
In addition, if the Hard Reset is caused by the assertion
of the
RST
pin, the following actions occur:
The Command register in the PCI configuration
space is cleared to zero. (No other register in the
configuration space is affected.)
The DMA CCB registers are set to their default
values.
Soft Reset: (S)
This reset occurs either when the
SCSI^RST
pin on the
SCSI bus is asserted or when the Reset SCSI Bus com-
mand is issued (by writing 03h to the SCSI command
register at ((B) = 0ch)).
Soft reset causes the following actions to occur:
All SCSI bus signals except
SCSI^RST
are
released.
The chip is returned to the Disconnected state.
An interrupt is generated if bit 6 in Control Register
One is enabled.
Disconnected Reset: (D)
Disconnected reset occurs when either of the following
conditions occur:
The Am79C974 is the Initiator and the SCSI bus
moves to a Bus Free state
The Selection command terminates due to
selection time-out
Disconnected reset causes the following actions:
All SCSI signals except
SCSI^RST
are deasserted.
The SCSI Command Register is initialized to
empty.
The IS1 and IS0 bits in the Internal State Register,
((B)+18h), are cleared to 0.
Please refer to the Technical Manual(PID #18738A) for
the default values for all registers.
Device Commands
The device commands can be broadly divided into two
categories, DMA commands and non-DMA commands.
DMA commands are those which cause data movement
between the host memory and the SCSI bus while non-
DMA commands are those that cause data movement
between the SCSI FIFO and the SCSI bus. The Most
Significant Bit of the command byte differentiates the
DMA from the non-DMA commands.
When a DMA command is issued, the contents of the
Start Transfer Count Register will be loaded into the
Current Transfer Count Register. Data transmission will
相關(guān)PDF資料
PDF描述
AM79C974KCW PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
AM79C975 PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973 PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C974KC 制造商:Advanced Micro Devices 功能描述:
AM79C974KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C974KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
AM79C975 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*