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參數(shù)資料
| 型號(hào)： | AM79C974 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | PCnetTM -的SCSI結(jié)合以太網(wǎng)和SCSI控制器PCI系統(tǒng) |
| 文件頁(yè)數(shù)： | 70/153頁(yè) |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974 |
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AMD
P R E L I M I N A R Y
70
Am79C974
The 544 bit count is derived from the following:
Minimum frame
size (excluding
preamble,
including FCS)
64
bytes
512
bits
Preamble/SFD size
8
bytes
64
bits
FCS size
4
bytes
32
bits
To be classed as a minimum size frame at the receiver,
the transmitted frame must contain:
Preamble + (Min Frame Size + FCS) bits
At the point that FCS is to be appended, the transmitted
frame should contain:
Preamble + (Min Frame Size – FCS) bits
64 + (512 – 32) bits
A minimum length transmit frame from the Am79C974
controller will therefore be 576 bits, after the FCS is
appended.
The Ethernet specification assumes that minimum
length messages will be at least 64 bytes in length.
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS bit in
CSR15. When DXMTFCS = 0 the transmitter will gener-
ate and append the FCS to the transmitted frame. If the
automatic padding feature is invoked (APAD_XMT is
set in CSR4), the FCS will be appended by the
Am79C974 controller regardless of the state of
DXMTFCS. Note that the calculated FCS is transmitted
most significant bit first. The default value of DXMTFCS
is 0 after H_RESET.
Transmit Exception Conditions
Exception conditions for frame transmission fall into two
distinct categories. Those which are the result of normal
network operation, and those which occur due to abnor-
mal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the Am79C974 controller include colli-
sions within the slot time with automatic retry. The
Am79C974 controller will ensure that collisions which
occur within 512 bit times from the start of transmission
(including preamble) will be automatically retried with no
host intervention. The transmit FIFO ensures this by
guaranteeing that data contained within the FIFO will
not be overwritten until at least 64 bytes (512 bits) of pre-
amble plus address, length and data fields have been
transmitted onto the network without encountering
acollision.
If 16 total attempts (initial attempt plus 15 retries) fail, the
Am79C974 controller sets the RTRY bit in the current
transmit TDTE in host memory (TMD2), gives up
ownership (resets the OWN bit to ZERO) for this frame,
and processes the next frame in the transmit ring for
transmission.
Abnormal network conditions include:
Loss of carrier.
Late collision.
SQE Test Error. (does not apply to 10BASE-Tport)
These should not occur on a correctly configured 802.3
network, and will be reported if they do.
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be reset until the STP (the next frame)
is found.
Loss of Carrier
A loss of carrier condition will be reported if the
Am79C974 controller cannot observe receive activity
whilst it is transmitting on the AUI port. After the
Am79C974 controller initiates a transmission it will ex-
pect to see data “l(fā)ooped-back” on the DI
±
pair. This will
internally generate a “carrier sense”, indicating that the
integrity of the data path to and from the MAU is intact,
and that the MAU is operating correctly. This “carrier
sense” signal must be asserted about 6 bit times before
the last transmitted bit on DO
±
. If “carrier sense” does
not become active in response to the data transmission,
or becomes inactive before the end of transmission, the
loss of carrier (LCAR) error bit will be set in TMD2 after
the frame has been transmitted. The frame will not be
re-tried on the basis of an LCAR error.
When the 10BASE-T port is selected, LCAR will be re-
ported for every packet transmitted during the Link
failcondition.
Late Collision
A late collision will be reported if a collision condition oc-
curs after one slot time (512 bit times) after the transmit
process was initiated (first bit of preamble commenced).
The Am79C974 controller will abandon the transmit
process for the particular frame, set Late Collision
(LCOL) in the associated TMD2, and process the next
transmit frame in the ring. Frames experiencing a late
collision will not be re-tried. Recovery from this condition
must be performed by upper layer software.
SQE Test Error
During the inter packet gap time following the comple-
tion of a transmitted message, the AUI CI
±
pair is as-
serted by some transceivers as a self-test. The integral
Manchester Encoder/Decoder will expect the SQE Test
Message (nominal 10 MHz sequence) to be returned via
the CI
±
pair, within a 40 network bit time period after DI
±
goes inactive (this does not apply if the 10BASE-T port
is selected). If the CI
±
input is not asserted within the 40
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C974KCW | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C975 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C974KC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C974KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C974KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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