參數(shù)資料
型號(hào)： AM79C974
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
中文描述： PCnetTM -的SCSI結(jié)合以太網(wǎng)和SCSI控制器PCI系統(tǒng)
文件頁數(shù)： 149/153頁
文件大?。?/td> 838K
代理商： AM79C974
AMD
A M E N D M E N T
15
Am79C974
DMA Registers
The following is a summary of the DMA register set or
the DMA Channel Context Block (DMA CCB). These
registers control the specifics for DMA operations such
as transfer length and scatter-gather options. The three
read-only working counter registers allow the system
software and driver to monitor the DMA transaction.
Each register address is represented by the PCI Con-
figuration Base Address (B) and its corresponding offset
value. The Base address for the Am79C974 is stored at
register address (10h) in the PCI configuration space.
Table 6. The DMA Registers
Register Acronym
Addr (Hex)
Register Description
Command
(bits 31:8 reserved, bits 7:0 used)
Starting Transfer Count
(bits 31:24 reserved, bits 23:0 used)
Starting Physical Address
(bits 31:0 used)
Working Byte Counter
Working Address Counter
(bits 31:0 used)
Status Register
(bits 31:8 reserved, bits 7:0 used)
Starting Memory Descriptor List (MDL) Address
Working MDL Counter
Type
CMD
(B)+40
R/W
STC
(B)+44
R/W
SPA
WBC
(B)+48
(B)+4C
R/W
R
WAC
(B)+50
R
STATUS
SMDLA
WMAC
(B)+54
(B)+58
(B)+5C
R
R/W
R
Command Register (CMD)
The upper 3 bytes of Command register are reserved,
the remaining (LSB) byte is defined as follows:
Address (B)+40h, LSB
7
6
READ/WRITE
1
DIR
INTE_D
INTE_P
MDL
Reserved Reserved
CMD1
CMD0
5
4
3
2
0
DIR:
Data transfer direction bit.
INTE_D:
DMA transfer active interrupt bit.
INTE_P:
Page transfer active interrupt bit.
MDL:
Memory Descriptor List (MDL) SPA enable bit.
RESERVED:
Reserved for future expansion. The zero value must be
written in these bits.
CMD1-0:
These two bits are encoded to represent four com-
mands: IDLE, BLAST, START, and ABORT.
CMD1
0
CMD0
0
Command
IDLE
Description
Resets the DMA block to the IDLE state. Stops any current transfer. Does not
affect status bits or cause an interrupt.
Empties all data bytes in DMA FIFO to memory during a DMA
write operation. Upon completion, the ‘BCMPLT’ bit will be set
in the DMA Status register. This command should not be used
during a DMA read operation.
Terminates the current DMA transfer. The DMA engine
should be restored to the ‘IDLE’ state following execution of
this command.
Note
: This is only valid after a ‘START’ command is issued.
Initiates a new DMA transfer. These bits must remain set
throughout the DMA operation until the ‘DONE’ bit in the DMA
Status Register is set.
Note:
This command should be issued only after all other
control bits have been initialized.
0
1
BLAST
1
0
ABORT
1
1
START
相關(guān)PDF資料
PDF描述
AM79C974KCW PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
AM79C975 PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973 PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C974KC 制造商:Advanced Micro Devices 功能描述:
AM79C974KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C974KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
AM79C975 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
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