- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄358698 > CY8C24123 Embedded Processors and Controllers PDF資料下載
參數(shù)資料
| 型號(hào)： | CY8C24123 |
| 英文描述： | Embedded Processors and Controllers |
| 中文描述： | 嵌入式處理器和控制器 |
| 文件頁(yè)數(shù)： | 252/322頁(yè) |
| 文件大?。?/td> | 3134K |
| 代理商： | CY8C24123 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)當(dāng)前第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)第316頁(yè)第317頁(yè)第318頁(yè)第319頁(yè)第320頁(yè)第321頁(yè)第322頁(yè)
Switched Capacitor Block
CY8C24xxx Preliminary Data Sheet
252
Document No. 38-12011 Rev. *E
December 22, 2003
Analog Switch Cap Type C PSoC Block
Control Registers
22.3.1
ASCxxCR0 Register
Bit 7: FCap.
This bit controls the size of the switched feed-
back capacitor in the integrator.
Bit 6: ClockPhase.
This bit controls the internal clock
phasing relative to the input clock phasing. ClockPhase
affects the output of the analog column bus, which is con-
trolled by the AnalogBus bit in Control 2 Register
(ASC10CR2, ASC21CR2).
Bit[6] is the ClockPhase select that inverts the clock internal
to the blocks. During normal operation of an SC block for the
amplifier of a column enabled to drive the output bus, the
connection is only made for the last half of PHI2 (during
PHI1 and for the first half of PHI2, the output bus floats at
the last voltage to which it was driven). This forms a sample
and hold operation using the output bus and its associated
capacitance. This design prevents the output bus from being
perturbed by the intermediate states of the SC operation
(often a reset state for PHI1 and settling to the valid state
during PHI2).
Following are the exceptions: 1) If the ClockPhase bit in
CR0 (for the SC block in question) is set to 1, then the out-
put is enabled for the whole of PHI2. 2) If the SHDIS signal
is set in bit 6 of the Analog Clock Source Control Register,
then sample and hold operation is disabled for all columns
and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their
respective PHI2s.
This bit also affects the latching of the comparator output
(CBUS). Both clock phases, PHI1 and PHI2, are involved in
the output latching mechanism. The capture of the next
value to be output from the latch (capture point event) hap-
pens during the falling edge of one clock phase, and the ris-
ing edge of the other clock phase will cause the value to
come out (output point event). This bit determines which
clock phase triggers the capture point event, and the other
clock will trigger the output point event. The value output to
the comparator bus will remain stable between output point
events.
Bit 5: ASign.
This bit controls the switch phasing of the
switches on the bottom plate of the ACap capacitor. The bot-
tom plate samples the input or the reference.
Bits 4 to 0: ACap[4:0].
The ACap bits set the value of the
capacitor in the A path.
For additional information, reference the
ASCxxCR0 register
on page 112
.
22.3.2
ASCxxCR1 Register
Bits 7, 6, and 5: ACMUX[2:0].
ACMux controls the input
muxing for both the A and C capacitor branches. The high
order bit, ACMux[2], selects one of two inputs for the C
branch.
Bits 4 to 0: BCap[4:0].
The BCap bits set the value of the
capacitor in the B path.
For additional information, reference the
ASCxxCR1 register
on page 113
.
22.3.3
ASCxxCR2 Register
Bit 7: AnalogBus.
This bit gates the output to the analog
column bus. The output on the analog column bus is
affected by the state of the ClockPhase bit in Control 0 Reg-
ister (ASC10CR0, ASC21CR0). If AnalogBus is set to 0, the
output to the analog column bus is tri-stated. If AnalogBus is
set to 1, the signal that is output to the analog column bus is
selected by the ClockPhase bit. If the ClockPhase bit is 0,
the block output is gated by sampling clock on last part of
PHI2. If the ClockPhase bit is 1, the block output continu-
ously drives the analog column bus (ABUS).
Bit 6: CompBus.
This bit controls the output to the column
comparator bus (CBUS). Note that if the comparator bus is
not driven by anything in the column, it is pulled low. The
comparator output is evaluated on the rising edge of internal
PHI1 and is latched so it is available during internal PHI2.
Bit 5: AutoZero.
This bit controls the shorting of the output
to the inverting input of the opamp. When shorted, the
opamp is basically a follower. The output is the opamp off-
set. By using the feedback capacitor of the integrator, the
block can memorize the offset and create an offset cancella-
tion scheme. AutoZero also controls a pair of switches
between the A and B branches and the summing node of
the opamp. If AutoZero is enabled, then the pair of switches
is active. AutoZero also affects the function of the FSW1 bit
in Control 3 Register.
Bits 4 to 0: CCap[4:0].
The CCap bits set the value of the
capacitor in the C path.
For additional information, reference the
ASCxxCR2 register
on page 114
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY93422ADC | x4 SRAM |
| CY93422ALC | x4 SRAM |
| CY93422ALMB | x4 SRAM |
| CY93422DC | x4 SRAM |
| CY93422DMB | x4 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY8C24123_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC? Programmable System-on-Chip? |
| CY8C24123-24PI | 功能描述:IC MCU 4K FLASH 256B 8-DIP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C24xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類(lèi)型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤(pán) |
| CY8C24123-24SI | 功能描述:IC MCU 4K FLASH 256B 8-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C24xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類(lèi)型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤(pán) |
| CY8C24123-24SIT | 功能描述:IC MCU 4K FLASH 256B 8-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C24xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類(lèi)型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤(pán) |
| CY8C24123A | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Mixed-Signal Array |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。