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參數(shù)資料
| 型號(hào)： | CY8C24123 |
| 英文描述： | Embedded Processors and Controllers |
| 中文描述： | 嵌入式處理器和控制器 |
| 文件頁數(shù)： | 55/322頁 |
| 文件大?。?/td> | 3134K |
| 代理商： | CY8C24123 |
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December 22, 2003
Document No. 38-12011 Rev. *E
55
CY8C24xxx Preliminary Data Sheet
Interrupt Controller
5.2
Register Definitions
Table 5-1
gives an overview of all registers related to inter-
rupt controller operation. The following text presents details
on the use of each register.
5.2.1
INT_CLRx Register
There are three interrupt clear registers (INT_CLR0,
INT_CLR1, and INT_CLR3) which may be referred to in
general as INT_CLRx. The INT_CLRx registers are similar
to the INT_MSKx registers in that they hold a bit for each
interrupt source. However, functionally the INT_CLRx regis-
ters are similar to the INT_VC register, although their opera-
tion is completely independent. When an INT_CLRx register
is read any bits that are set indicate an interrupt has been
posted for that hardware resource. Therefore, reading these
registers gives the user the ability to determine all posted
interrupts.
The way an individual bit value written to an INT_CLRx reg-
ister is interpreted is determined by the Enable Software
Interrupt (ENSWINT) bit in INT_MSK3[7]. When ENSWINT
is cleared (the default state) writing 1's to an INT_CLRx reg-
ister has no effect. However, writing 0's to an INT_CLRx reg-
ister, when ENSWINT is cleared, will cause the
corresponding interrupt to be cleared. If the ENSWINT bit is
set, any 0's written to the INT_CLRx registers will be
ignored. However, 1's written to an INT_CLRx register, while
ENSWINT is set, will cause an interrupt to be posted for the
corresponding interrupt. Enabling software interrupts allows
a user's code to create software interrupts that can aid in
debugging interrupt service routines, by eliminating the
need to create the system level interactions that may be
necessary to create a hardware interrupt.
For additional information, reference the
INT_CLR0 register
on page 131
, the
INT_CLR1 register on page 133
, and the
INT_CLR3 register on page 134
.
5.2.2
INT_MSKx Register
There are three interrupt mask registers (INT_MSK0,
INT_MSK1, and INT_MSK3) which may be referred to in
general as INT_MSKx. If cleared, each bit in an INT_MSKx
register prevents an interrupt from becoming a pending
interrupt (input to the priority encoder). However, an inter-
rupt may still post even if its mask bit is zero. All INT_MSKx
bits are independent of all other INT_MSKx bits. If an
INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that will become a
pending interrupt. For example, if INT_MSK0[5] is set and at
least one GPIO pin is configured to generate an interrupt,
the interrupt controller will allow a GPIO interrupt request to
post and become a pending interrupt for the M8C to respond
to. If a higher priority interrupt is generated before the M8C
responds to the GPIO interrupt, the higher priority interrupt
will be pending and not the GPIO interrupt. INT_MSK3[7]
(ENSWINT) is a special non-mask bit that controls the
behavior of the INT_CLRx registers. See the INT_CLRx reg-
ister in this section for more information.
Each interrupt source may require configuration at a block
level. Refer to other chapters of this document for informa-
tion on how to configure an individual interrupt source.
For additional information, reference the
INT_MSK0 register
on page 136
, the
INT_MSK1 register on page 137
, and the
INT_MSK3 register on page 135
.
5.2.3
INT_VC Register
The interrupt vector clear register (INT_VC) performs two
different functions. When the register is read, the least sig-
nificant byte of the highest priority pending interrupt is
returned. For example, if the GPIO and I
2
C interrupts were
pending and the INT_VC register was read, the value 1Ch
would be read. However, if no interrupt were pending, the
value 00h would be returned. This is the reset vector in the
interrupt table; however, reading 00h from the INT_VC reg-
ister should not be considered to be an indication that a sys-
tem reset is pending. Rather, reading 00h from the INT_VC
register simply indicates that there are no pending inter-
rupts. The highest priority interrupt, indicated by the value
returned by a read of the INT_VC register, is removed from
the list of pending interrupts when the M8C performs an
Interrupt Vector Read (IVR). The clear of the highest priority
pending interrupt occurs asynchronously.
Reading the INT_VC has limited usefulness. If interrupts are
enabled, a read to the INT_VC register would not be able to
determine that an interrupt was pending before the interrupt
was actually taken. However, while in an interrupt, a user
may wish to read the INT_VC register to see what the next
interrupt will be. When the INT_VC register is written, with
any value, all pending and posted interrupts are cleared by
asserting the clear line for each interrupt.
For additional information, reference the
INT_VC register on
page 138
.
5.2.4
CPU_F Register
Only the GIE bit in the CPU_F register is related to the inter-
rupt controller. This bit is the Global Interrupt Enable. When
this bit is set, the M8C will take a pending interrupt. When
the GIE bit is cleared, the M8C will not take any interrupts.
By default, this bit is cleared. To set or clear this bit, the
AND
F, expr,
or
OR F, expr,
or
XOR F, expr
instructions must be
used. (Written another way:
AND
/
OR
/X
OR
F, expr
instruc-
tions must be used.) The GIE flag bit is covered in more
detail in the chapter titled
“CPU Core (M8C)” on page 37
.
For additional information, reference the
CPU_F register on
page 152
.
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| CY8C24123_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC? Programmable System-on-Chip? |
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