參數資料
型號： DSPA56371
廠商： 飛思卡爾半導體(中國)有限公司
元件分類： 數字信號處理
英文描述： SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述： SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個DAC
文件頁數： 13/124頁
文件大?。?/td> 1752K
代理商： DSPA56371
Signal/Connection Descriptions
Freescale Semiconductor
DSP56371 Technical Data
11
3.2
Power
Figure 3.
VDD Connections
Table 2. Power Inputs
Power Name
Description
PLLA_VDD (1)
PLLP_VDD(1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors.
PLLD_VDD (1)
PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors.
CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
decoupling capacitors.
IO_VDD (5)
SHI, ESAI, ESAI_1, DAX and Timer I/O Power —The voltage (3.3 V) should be well-regulated
and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail.
This is an isolated power for the SHI, ESAI, ESAI_1, DAX and Timer I/O. The user must provide
adequate external decoupling capacitors.
60
FST_PE4
59
SDO5_SDI0_PE6
58
SDO4_SDI1_PE7
57
SDO3_SDI2_PE8
56
SDO2_SDI3_PE9
55
SDO1_PE10
54
SDO0_PE11
53
CORE_GND
52
CORE_VDD
51
MODB_IRQA
50
MODB_IRQB
49
MODC_IRQC
48
MODD_IRQD
47
RESET_B
46
PINIT_NMI
45
EXTAL
44
PLLD_VDD
43
PLLD_GND
42
PLLP_GND
41
PLLP_VDD
PF9
21
SC
A
N
22
PF1
0
23
IO
_GND
24
IO
_VDD
25
TIO0
_P
B0
26
TIO1
_P
B1
27
CORE
_GND
28
CORE
_V
DD
29
TDO
30
TDI
31
TCK
32
TMS
33
M
O
SI
_H
A0
34
MI
S
O
_
S
DA
35
SC
K
_
SC
L
36
SS
_H
A2
37
HRE
Q
38
PL
LA
_VD
D
39
PL
LA
_GN
D
40
SDO5_SDI0_PC7
1
IO_GND
2
IO_VDD
3
SDO3_SDI2_PC8
4
SDO2_SDI3_PC9
5
SDO1_PC10
6
SDO0_PC11
7
CORE_VDD
8
PF8
9
PF6
10
PF7
11
CORE_GND
12
PF2
13
PF3
14
PF4
15
PF5
16
IO_VDD
17
PF1
18
PF0
19
IO_GND
20
8
0
S
D
O
5
_S
DI
0_
P
C
6
79
FST_P
C
4
78
FSR_PC1
77
SC
KT_P
C
3
76
SC
KR
_P
C
0
75
IO_V
D
74
IO_G
N
D
73
HC
K
T
_PC
5
72
HC
K
R
_
P
C
2
71
CO
R
E
_V
DD
70
AC
I_P
D
0
69
AD
O_P
D
1
68
CO
R
E
_G
ND
67
H
C
KR
_P
E2
66
H
C
KT
_
P
E5
65
IO_G
N
D
64
IO_V
D
63
SC
KR
_P
E0
62
SC
KT_P
E3
61
FSR_PE
1
ESAI
ESAI_1
DAX
Int/Mod
PLL
SHI
OnCE
Timer
GPIO
3.3V
1.25V
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PDF描述
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