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| 型號(hào)： | DSPA56371 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個(gè)DAC |
| 文件頁(yè)數(shù)： | 92/124頁(yè) |
| 文件大?。?/td> | 1752K |
| 代理商： | DSPA56371 |
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DSP56371 Overview
Freescale Semiconductor
DSP56371 Technical Data
7
There are on-chip ROMs for program and bootstrap memory (64K x 24-bit), X ROM (32K x 24-bit) and Y ROM(32K x 24-bit).
More information on the internal memory is provided in DSP56371 User Manual, Section 3, MemorySection 3, .
2.4.8
Off-Chip Memory Expansion
Memory cannot be expanded off-chip. There is no external memory bus.
2.5
Peripheral Overview
The DSP56371 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core
features previously discussed, the DSP56371 provides the following peripherals:
As many as 39 dedicate or user-configurable general purpose input/output (GPIO) signals
Timer/event counter (TEC) module, containing three independent timers
Memory switch mode in on-chip memory
Four external interrupt/mode control lines and one external non-maskable interrupt line
Enhanced serial audio interface (ESAI) with up to four receivers and up to six transmitters, master or slave, using the
I2S, Sony, AC97, network and other programmable protocols
A second enhanced serial audio interface (ESAI_1) with up to four receivers and up to six transmitters, master or slave,
using the I2S, Sony, AC97, network and other programmable protocols.
Serial host interface (SHI) using SPI and I2C protocols, with multi-master capability, 10-word receive FIFO and support
for 8-, 16- and 24-bit words
A Digital audio transmitter (DAX): a serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU
digital audio formats
2.5.1
General Purpose Input/Output (GPIO)
The DSP56371 provides 11 dedicated GPIO and 28 programmable signals that can operate either as GPIO pins or peripheral
pins (ESAI, ESAI_1, DAX, and TEC). The signals are configured as GPIO after hardware reset. Register programming
techniques for all GPIO functionality among these interfaces are very similar and are described in the following sections.
2.5.2
Triple Timer (TEC)
This section describes a peripheral module composed of a common 21-bit prescaler and three independent and identical general
purpose 24-bit timer/event counters, each one having its own register set.
Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks). Two of
the three timers can signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers
after a specified number of events (clocks) occurred. Two of the three timers connect to the external world through bidirectional
pins (TIO0, TIO1). When a TIO pin is configured as input, the timer functions as an external event counter or can measure
external pulse width/signal period. When a TIO pin is used as output the timer is functioning as either a timer, a watchdog or a
Pulse Width Modulator. When a TIO pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer to
DSP56371 User Manual, Section 11, Triple Timer Module.
2.5.3
Enhanced Serial Audio Interface (ESAI)
The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-
standard codecs, other DSPs, microprocessors and peripherals that implement the Motorola SPI serial protocol. The ESAI
consists of independent transmitter and receiver sections, each with its own clock generator. It is a superset of the DSP56300
family ESSI peripheral and of the DSP56000 family SAI peripheral. For more information on the ESAI, refer to DSP56371 User
Manual, Section 8, Enhanced Serial Audio Interface (ESAI).
2.5.4
Enhanced Serial Audio Interface 1 (ESAI_1)
The ESAI_1 is a second ESAI interface. The ESAI_1 is functionally identical to ESAI. For more information on the ESAI_1, refer
to DSP56371 User Manual, Section 9, Enhanced Serial Audio Interface (ESAI_1).
2.5.5
Serial Host Interface (SHI)
The SHI is a serial input/output interface providing a path for communication and program/coefficient data transfers between the
DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface
directly to either of two well-known and widely used synchronous serial buses: the Motorola serial peripheral interface (SPI) bus
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