參數(shù)資料
型號(hào)： DSPA56371
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述： SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個(gè)DAC
文件頁(yè)數(shù)： 24/124頁(yè)
文件大小： 1752K
代理商： DSPA56371
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DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
3.3
Ground
3.4
SCAN
3.5
Clock and PLL
3.6
Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is
deasserted, these inputs are hardware interrupt request lines.
Table 3. Grounds
Ground Name
Description
PLLA_GND(1)
PLLP_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
PLLD_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
CORE_GND (4) Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
IO_GND (5)
SHI, ESAI, ESAI_1, DAX and Timer I/O Ground—IO_GND is an isolated ground for the SHI,
ESAI, ESAI_1, DAX and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Table 4. SCAN signals
Signal
Name
Type
State
during
Reset
Signal Description
SCAN
Input
SCAN—Manufacturing test pin. This pin should be pulled low.
Internal Pull down resistor.
Table 5. Clock and PLL Signals
Signal
Name
Type
State
during
Reset
Signal Description
EXTAL
Input
External Clock Input—An external clock source must be connected to EXTAL
in order to supply the clock to the internal clock generator and PLL.
This input cannot tolerate 5 V.
PINIT/NMI
Input
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion
and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is
a negative-edge-triggered nonmaskable interrupt (NMI) request internally
synchronized to internal system clock.
Internal Pull up resistor.
This input is 5 V tolerant.
相關(guān)PDF資料
PDF描述
DSR-09 PIANO DIP SWITCH-9SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT
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DP-10T PIANO DIP SWITCH-10SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-RIGHT ANGLE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSPA56371AF150 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 150MHZ 150MIPS 80-PIN LQFP TRAY - Trays
DSPA56371AF180 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 181MHZ 181MIPS 80-PIN LQFP TRAY - Trays
DSPA56720AG 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 200MHZ 200MIPS 144-PIN LQFP TRAY - Trays
DSPA56721AF 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 200MHZ 200MIPS 80-PIN LQFP TRAY - Bulk
DSPA56721AG 制造商:Freescale Semiconductor 功能描述:AUD PROCESSOR 144LQFP - Bulk
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