參數(shù)資料
型號: DSPA56371
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述: SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個DAC
文件頁數(shù): 44/124頁
文件大?。?/td> 1752K
代理商: DSPA56371
26
DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
3.10
SPDIF Transmitter Digital Audio Interface
SDO1_1
Output
GPIO
disconnected
Serial Data Output 1—SDO1_1 is used to transmit data from
the TX1 serial transmit shift register.
PE10
Input, output, or
disconnected
Port E10—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO0_1
Output
GPIO
disconnected
Serial Data Output 0—SDO0_1 is used to transmit data from
the TX0 serial transmit shift register.
PE11
Input, output, or
disconnected
Port E11—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Table 10. Digital Audio Interface (DAX) Signals
Signal
Name
Type
State During
Reset
Signal Description
ACI
Input
GPIO
Disconnected
Audio Clock Input—This is the DAX clock input. When
programmed to use an external clock, this input supplies the DAX
clock. The external clock frequency must be 256, 384, or 512
times the audio sampling frequency (256
× Fs, 384 × Fs or 512 ×
Fs, respectively).
PD0
Input,
output, or
disconnected
Port D0—When the DAX is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Table 9. Enhanced Serial Audio Interface_1 Signals
Signal Name
Signal Type
State during
Reset
Signal Description
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