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參數(shù)資料
| 型號： | DSPA56371 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個DAC |
| 文件頁數(shù)： | 33/124頁 |
| 文件大?。?/td> | 1752K |
| 代理商： | DSPA56371 |
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16
DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
SS
Input
Tri-stated
SPI Slave Select—This signal is an active low Schmitt-trigger input when
configured for the SPI mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer. When configured for the SPI
master mode, this signal should be kept deasserted (pulled high). If it is
asserted while configured as SPI master, a bus error condition is flagged. If SS
is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in
the high-impedance state.
HA2
Input
I2C Slave Address 2—This signal uses a Schmitt-trigger input when
configured for the I2C mode. When configured for the I2C Slave mode, the HA2
signal is used to form the slave device address. HA2 is ignored in the I2C
master mode.
This signal is tri-stated during hardware, software and individual reset. Thus,
there is no need for an external pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
HREQ
Input or
Output
Tri-stated
Host Request—This signal is an active low Schmitt-trigger input when
configured for the master mode but an active low output when configured for the
slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI
is ready for the next data word transfer and deasserted at the first clock pulse of
the new data word transfer. When configured for the master mode, HREQ is an
input. When asserted by the external slave device, it will trigger the start of the
data word transfer by the master. After finishing the data word transfer, the
master will await the next assertion of HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for an external
pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
Table 7. Serial Host Interface Signals (Continued)
Signal
Name
Signal
Type
State
during
Reset
Signal Description
相關PDF資料 |
PDF描述 |
|---|---|
| DSR-09 | PIANO DIP SWITCH-9SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
| DA-12 | PIANO DIP SWITCH-12SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-RIGHT ANGLE |
| DP-10T | PIANO DIP SWITCH-10SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-RIGHT ANGLE |
| DS-03T | PIANO DIP SWITCH-3SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
| DS-06 | PIANO DIP SWITCH-6SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSPA56371AF150 | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 150MHZ 150MIPS 80-PIN LQFP TRAY - Trays |
| DSPA56371AF180 | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 181MHZ 181MIPS 80-PIN LQFP TRAY - Trays |
| DSPA56720AG | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 200MHZ 200MIPS 144-PIN LQFP TRAY - Trays |
| DSPA56721AF | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 200MHZ 200MIPS 80-PIN LQFP TRAY - Bulk |
| DSPA56721AG | 制造商:Freescale Semiconductor 功能描述:AUD PROCESSOR 144LQFP - Bulk |
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