- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄171234 > DSPA56371 (飛思卡爾半導(dǎo)體(中國)有限公司) SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs PDF資料下載
參數(shù)資料
| 型號： | DSPA56371 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個DAC |
| 文件頁數(shù)： | 47/124頁 |
| 文件大小： | 1752K |
| 代理商： | DSPA56371 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
Signal/Connection Descriptions
Freescale Semiconductor
DSP56371 Technical Data
29
3.12
Timer
3.13
JTAG/OnCE Interface
Table 12. Timer Signal
Signal
Name
Type
State
during
Reset
Signal Description
TIO0
Input or
Output
GPIO Input Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input.
When timer 0 functions in watchdog, timer, or pulse modulation mode,
TIO0 is used as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer 0
control/status register (TCSR0). If TIO0 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input but connected
to VDD through a pull-up resistor in order to ensure a stable logic level
at this input.
Internal Pull down resistor.
This input is 5 V tolerant.
TIO1
Input or
Output
GPIO Input Timer 1 Schmitt-Trigger Input/Output—When timer 1 functions as an
external event counter or in measurement mode, TIO1 is used as input.
When timer 1 functions in watchdog, timer, or pulse modulation mode,
TIO1 is used as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer 1
control/status register (TCSR1). If TIO1 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input but connected
to Vdd through a pull-up resistor in order to ensure a stable logic level
at this input.
Internal Pull down resistor.
This input is 5 V tolerant.
Table 13. JTAG/OnCE Interface
Signal
Name
Signal
Type
State
during
Reset
Signal Description
TCK
Input
Test Clock—TCK is a test clock input signal used to synchronize the JTAG
test logic. It has an internal pull-up resistor.
Internal Pull up resistor.
This input is 5 V tolerant..
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSR-09 | PIANO DIP SWITCH-9SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
| DA-12 | PIANO DIP SWITCH-12SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-RIGHT ANGLE |
| DP-10T | PIANO DIP SWITCH-10SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-RIGHT ANGLE |
| DS-03T | PIANO DIP SWITCH-3SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
| DS-06 | PIANO DIP SWITCH-6SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSPA56371AF150 | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 150MHZ 150MIPS 80-PIN LQFP TRAY - Trays |
| DSPA56371AF180 | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 181MHZ 181MIPS 80-PIN LQFP TRAY - Trays |
| DSPA56720AG | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 200MHZ 200MIPS 144-PIN LQFP TRAY - Trays |
| DSPA56721AF | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 200MHZ 200MIPS 80-PIN LQFP TRAY - Bulk |
| DSPA56721AG | 制造商:Freescale Semiconductor 功能描述:AUD PROCESSOR 144LQFP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。