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參數(shù)資料
| 型號： | DSPA56371 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個DAC |
| 文件頁數(shù)： | 41/124頁 |
| 文件大?。?/td> | 1752K |
| 代理商： | DSPA56371 |
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Signal/Connection Descriptions
Freescale Semiconductor
DSP56371 Technical Data
23
FSR_1
Input or output
GPIO
disconnected
Frame Sync for Receiver_1—This is the receiver frame sync
input/output signal. In the asynchronous mode (SYN=0), the
FSR_1 pin operates as the frame sync input or output used by
all the enabled receivers. In the synchronous mode (SYN=1), it
operates as either the serial flag 1 pin (TEBE=0), or as the
transmitter external buffer enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR_1 register. When
configured as the output flag OF1, this pin will reflect the value
of the OF1 bit in the SAICR_1 register, and the data in the OF1
bit will show up at the pin synchronized to the frame sync in
normal mode or the slot in network mode. When configured as
the input flag IF1, the data value at the pin will be stored in the
IF1 bit in the SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
PE1
Input, output, or
disconnected
Port E1—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
FST_1
Input or output
GPIO
disconnected
Frame Sync for Transmitter_1—This is the transmitter frame
sync input/output signal. For synchronous mode, this signal is
the frame sync for both transmitters and receivers. For
asynchronous mode, FST_1 is the frame sync for the
transmitters only. The direction is determined by the transmitter
frame sync direction (TFSD) bit in the ESAI_1 transmit clock
control register (TCCR_1).
PE4
Input, output, or
disconnected
Port E4—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Table 9. Enhanced Serial Audio Interface_1 Signals
Signal Name
Signal Type
State during
Reset
Signal Description
相關(guān)PDF資料 |
PDF描述 |
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| DSR-09 | PIANO DIP SWITCH-9SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
| DA-12 | PIANO DIP SWITCH-12SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-RIGHT ANGLE |
| DP-10T | PIANO DIP SWITCH-10SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-RIGHT ANGLE |
| DS-03T | PIANO DIP SWITCH-3SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
| DS-06 | PIANO DIP SWITCH-6SWITCHES, SPST, LATCHED,0.05A, 24VDC, THROUGH HOLE-STRAIGHT |
相關(guān)代理商/技術(shù)參數(shù) |
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| DSPA56371AF150 | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 150MHZ 150MIPS 80-PIN LQFP TRAY - Trays |
| DSPA56371AF180 | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 181MHZ 181MIPS 80-PIN LQFP TRAY - Trays |
| DSPA56720AG | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 200MHZ 200MIPS 144-PIN LQFP TRAY - Trays |
| DSPA56721AF | 制造商:Freescale Semiconductor 功能描述:DSP FIXED-POINT 24-BIT 200MHZ 200MIPS 80-PIN LQFP TRAY - Bulk |
| DSPA56721AG | 制造商:Freescale Semiconductor 功能描述:AUD PROCESSOR 144LQFP - Bulk |
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