參數(shù)資料
型號(hào): DSPA56371
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號(hào)處理
英文描述: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述: SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個(gè)DAC
文件頁數(shù): 54/124頁
文件大?。?/td> 1752K
代理商: DSPA56371
External Clock Operation
Freescale Semiconductor
DSP56371 Technical Data
35
10
External Clock Operation
The DSP56371 system clock is an externally supplied square wave voltage source connected to EXTAL (see Figure 4).
.
Figure 4.
External Clock Timing
Table 18. Clock Operation 150 and 181 MHz Values
No.
Characteristics
Symbol
150 MHz
181 MHz
Min
Max
Min
Max
6
EXTAL input high 1,2
(40% to 60% duty cycle)
Eth
3.33ns
100ns
2.75ns
100ns
7
EXTAL input low1,2
(40% to 60% duty cycle)
Etl
3.33ns
100ns
2.75ns
100ns
8
EXTAL cycle time2
With PLL disabled
With PLL enabled
Etc
6.66ns
inf
200ns
5.52ns
inf
200ns
9
Instruction cycle time= ICYC = TC
3
With PLL disabled
With PLL enabled
Icyc
6.66ns
inf
13.0ns
5.52ns
inf
13.0ns
Notes:
1. Measured at 50% of the input transition
2. The maximum value for PLL enabled is given for minimum VCO and maximum MF.
3. The maximum value for PLL enabled is given for minimum VCO and maximum DF.
4. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low
time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower
clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time
and low time requirements are met.
EXTAL
VIL
VIH
Midpoint
Note:
The midpoint is 0.5 (VIH + VIL).
ETH
ETL
ETC
7
8
6
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