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參數(shù)資料
| 型號(hào)： | DSPA56371 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個(gè)DAC |
| 文件頁數(shù)： | 55/124頁 |
| 文件大?。?/td> | 1752K |
| 代理商： | DSPA56371 |
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36
DSP56371 Technical Data
Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
11
Reset, Stop, Mode Select, and Interrupt Timing
Table 19. Reset, Stop, Mode Select, and Interrupt Timing
No.
Characteristics
Expression
Min
Max
Unit
10
Delay from RESET assertion to all output pins at
reset value3
——
11
ns
11
Required RESET duration4
Power on, external clock generator, PLL
disabled
2 x TC
11.1
—
ns
Power on, external clock generator, PLL
enabled
2 x TC
11.1
--
ns
12
Syn reset setup time from RESET
Maximum
TC
—5.5
ns
13
Syn reset de assert delay time
Minimum
Maximum(PLL enabled)
2
× TC
(2xTC)+TLOCK
11.1
5.0
—ns
ms
14
Mode select setup time
10.0
—
ns
15
Mode select hold time
10.0
—
ns
16
Minimum edge-triggered interrupt request
assertion width
2 xTC
11.1
—
ns
17
Minimum edge-triggered interrupt request
deassertion width
2 xTC
11.1
—
ns
18
Delay from interrupt trigger to interrupt code
execution.
10 xTC + 5
60.0
ns
19
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop)2, 3
PLL is active during Stop and Stop delay is
enabled
(OMR Bit 6 = 0)
9+(128K
× TC)704
—
us
PLL is active during Stop and Stop delay is
not enabled
(OMR Bit 6 = 1)
25
× TC
138
—
ns
PLL is not active during Stop and Stop delay
is enabled (OMR Bit 6 = 0)
9+(128KxTC)+Tlock
5.7
ms
PLL is not active during Stop and Stop delay
is not enabled (OMR Bit 6 = 1)
(25 x TC)+Tlock
5ms
20
Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to general-purpose transfer
output valid caused by first interrupt
instruction execution
10 x TC + 3.0
59.0
ns
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