參數(shù)資料
型號: DSPA56371
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述: SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個DAC
文件頁數(shù): 53/124頁
文件大?。?/td> 1752K
代理商: DSPA56371
34
DSP56371 Technical Data
Freescale Semiconductor
AC Electrical Characteristics
8
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8V and a VIH
minimum of 2.0V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production
with respect to the 50% point of the respective input signal’s transition. DSP56371 output levels are measured with the production
test machine VOL and VOH reference levels set at 1.0V and 1.8V, respectively.
NOTE
Although the minimum value for the frequency of EXTAL is 0 MHz (PLL bypassed), the
device AC test conditions are 5 MHz and rated speed.
9
Internal Clocks
Table 17. INTERNAL CLOCKS
No.
Characteristics
Symbol
Min
Typ
Max
UNIT
Condition
1
Comparison Frequency
Fref1
5
--
20
MHZ
Fref = FN/NR
2
Input Clock Frequency
FIN
Fref*NR
NR is input divider
value
3
Output clock Frequency (with
PLL enabled2,3
FOUT
75
(1000/Etc
× MF x
FM)/
(PDF
× DF x OD)
--
MHZ
FOUT=FVCO/NO
where NO is output
divider value
4
Output clock Frequency (with
PLL disabled2,3
FOUT
--
1000/Etc
--
MHZ
---
5
Duty Cycle
--
40
50
60
%
FVCO=300MHZ~60
0MHZ
Notes:
1. See users manual for definition.
2. DF = Division Factor
Ef = External frequency
MF = Multiplication Factor
PDF = Predivision Factor
FM= Feedback Multiplier
OD = Output Divider
3. Maximum frequency will vary depending on the ordered part number.
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