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參數(shù)資料
| 型號： | GE28F640W30B85 |
| 英文描述： | EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC |
| 中文描述： | 的EEPROM | FLASH動畫| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 11/91頁 |
| 文件大?。?/td> | 994K |
| 代理商： | GE28F640W30B85 |
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1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
11
2.3
Signal Descriptions
Table 1
describes ball usage.
Table 1.
Signal Descriptions
Symbol
Type
Name and Function
A[22:0]
I
ADDRESS INPUTS:
For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]
D[15:0]
I/O
DATA INPUTS/OUTPUTS:
Inputs data and commands during write cycles; outputs data during
memory, status register, protection register, and configuration code reads. Data pins float when the
chip or outputs are deselected. Data is internally latched during writes.
ADV#
I
ADDRESS VALID:
ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on ADV#’s rising edge or CLK’s rising (or falling) edge,
whichever occurs first.
CE#
I
CHIP ENABLE:
Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the device, places it in standby mode, and tri-states all outputs.
CLK
I
CLOCK:
CLK synchronizes the device to the system bus frequency during synchronous reads and
increments an internal address generator. During synchronous read operations, addresses are latched
on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.
OE#
I
OUTPUT ENABLE:
When asserted, OE# enables the device’s output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
RST#
I
RESET:
When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. de-asserting RST# enables normal operation and places the
device in asynchronous read-array mode.
WAIT
O
WAIT:
The WAIT signal indicates valid data during synchronous read modes. It can be configured to be
asserted-high or asserted-low based on bit 10 of the Configuration Register. WAIT is tri-stated if CE# is
deasserted. WAIT is not gated by OE#.
WE#
I
WRITE ENABLE:
WE# controls writes to the CUI and array. Addresses and data are latched on the
rising edge of WE#.
WP#
I
WRITE PROTECT:
Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
Section 7.1, “Block Lock Operations” on page 36
for details on block locking.
VPP
Pwr/I
ERASE AND PROGRAM POWER:
A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V
PP
≤
V
PPLK
. Block erase and program at invalid V
PP
voltages should
not be attempted.
Set V
PP
= V
CC
for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the V
IH
level of V
PP
can be as low as V
PP1
min. V
PP
must remain above V
PP1
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V may reduce block cycling capability.
VCC
Pwr
DEVICE POWER SUPPLY:
Writes are inhibited at V
CC
≤
V
LKO
. Device operations at invalid V
CC
voltages should not be attempted.
VCCQ
Pwr
OUTPUT POWER SUPPLY:
Enables all outputs to be driven at V
CCQ
. This input may be tied directly to
VCC.
VSS
Pwr
GROUND:
Pins for all internal device circuitry must be connected to system ground.
VSSQ
Pwr
OUTPUT GROUND
: Provides ground to all outputs which are driven by VCCQ. This signal may be tied
directly to VSS.
DU
DON’T USE:
Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins and must be floated.
NC
NO CONNECT:
No internal connection; can be driven or floated.
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