參數(shù)資料
型號(hào): GE28F640W30B85
英文描述: EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
中文描述: 的EEPROM | FLASH動(dòng)畫| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料
文件頁(yè)數(shù): 27/91頁(yè)
文件大?。?/td> 994K
代理商: GE28F640W30B85
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
27
The 12-V V
PP
mode enhances programming performance during the short time period typically
found in manufacturing processes; however, it is not intended for extended use.12 V may be
applied to V
PP
during program and erase operations as specified in
Section 10.2, “Operating
Conditions” on page 55
. VPP may be connected to 12 V for a total of t
PPH
hours maximum.
Stressing the device beyond these limits may cause permanent damage.
5.3
Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of enhancements
to the conventional 12 Volt word program algorithm. EFP's more efficient WSM algorithm
eliminates the traditional overhead delays of the conventional word program mode in both the host
programming system and the flash device. Changes to the conventional word programming
flowchart and internal WSM routine were developed because of today's beat-rate-sensitive
manufacturing environments; a balance between programming speed and cycling performance was
attained.
The host programmer writes data to the device and checks the Status Register to determine when
the data has completed programming. This modification essentially cuts write bus cycles in half.
Following each internal program pulse, the WSM increments the device's address to the next
physical location. Now, programming equipment can sequentially stream program data throughout
an entire block without having to setup and present each new address. In combination, these
enhancements reduce much of the host programmer overhead, enabling more of a data streaming
approach to device programming.
EFP further speeds up programming by performing internal code verification. With this, PROM
programmers can rely on the device to verify that it has been programmed properly. From the
device side, EFP streamlines internal overhead by eliminating the delays previously associated to
switch voltages between programming and verify levels at each memory-word location.
EFP consists of four phases: setup, program, verify and exit. Refer to
Figure 6, “Enhanced Factory
Program Flowchart” on page 30
for a detailed graphical representation of how to implement EFP.
5.3.1
EFP Requirements and Considerations
EFP requirements:
Ambient temperature: T
A
= 25 °C ±5 °C
V
CC
within specified operating range
V
PP
within specified V
PP2
range
Target block unlocked
EFP considerations:
Block cycling below 100 erase cycles
1
RWW not supported
2
EFP programs one block at a time
EFP cannot be suspended
相關(guān)PDF資料
PDF描述
GE28F640W30T70 EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
GE28F640W30T85 EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
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