參數(shù)資料
型號(hào)： GE28F640W30B85
英文描述： EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
中文描述： 的EEPROM | FLASH動(dòng)畫| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料
文件頁數(shù)： 53/91頁
文件大?。?/td> 994K
代理商： GE28F640W30B85
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
53
9.3
Standby Power
With CE# at V
IH
and the device in read mode, the flash memory is in standby mode, which disables
most device circuitry and substantially reduces power consumption. Outputs are placed in a high
-
impedance state independent of the OE# signal state. If CE# transitions to V
IH
during erase or
program operations, the device continues the operation and consumes corresponding active power
until the operation is complete. ICCS is the average current measured over any 5 ms time interval 5
μs after a CE# de-assertion.
9.4
Power-Up/Down Characteristics
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required if V
CC
, V
CCQ
, and V
PP
are connected together; so it
doesn’t matter whether V
PP
or V
CC
powers-up first. If V
CCQ
and/or V
PP
are not connected to the
system supply, then V
CC
should attain V
CCMIN
before applying VCCQ and VPP. Device inputs
should not be driven before supply voltage = V
CCMIN.
Power supply transitions should only occur
when RST# is low.
9.4.1
System Reset and RST#
The use of RST# during system reset is important with automated program/erase devices because
the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. To allow proper CPU/flash initialization
at system reset, connect RST# to the system CPU RESET# signal.
System designers must guard against spurious writes when VCC voltages are above V
LKO
.
Because both WE# and CE# must be low for a command write, driving either signal to V
IH
inhibits
writes to the device. The CUI architecture provides additional protection because alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RST# is brought to V
IH
, regardless of its control input states. By
holding the device in reset (RST# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
9.4.2
VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software and is not altered by VPP or CE# transitions
or WSM actions. Read-array mode is its power-up default state after exit from reset mode or after
VCC transitions above V
LKO
(Lockout voltage).
After completing program or block erase operations (even after VPP transitions below V
PPLK
), the
Read Array command must reset the CUI to read-array mode if flash memory array access is
desired.
相關(guān)PDF資料
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GE28F640W30T85 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
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