1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
8
Datasheet
Signal
names are in all CAPS (see
Section 2.3, “Signal Descriptions” on page 11
.)
Voltage
applied to the signal is subscripted, for example, V
PP
.
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify
these references, the following conventions have been adopted:
A
block
is a group of bits (or words) that erase simultaneously with one block erase
instruction.
A
main block
contains 32 Kwords.
A
parameter block
contains 4 Kwords.
The
Block Base Address
(BBA) is the first address of a block.
A
partition
is a group of blocks that share erase and program circuitry and a common status
register.
The
Partition Base Address
(PBA) is the first address of a partition. For example, on a 32-
Mbit top-parameter device, partition number 5 has a PBA of 140000h.
The
top partition
is located at the highest physical device address. This partition may be a
main partition or a parameter partition.
The
bottom partition
is located at the lowest physical device address. This partition may be a
main partition or a parameter partition.
A
main partition
contains only main blocks.
A
parameter partition
contains a mixture of main blocks and parameter blocks.
A
top parameter device
(
TPD
) has the parameter partition at the top of the memory map with
the parameter blocks at the top of that partition. This was formerly referred to as top-boot
device.
A
bottom parameter device
(
BPD
) has the parameter partition at the bottom of the memory
map with the parameter blocks at the bottom of that partition. This was formerly referred to as
bottom-boot block flash device.
2.0
Device Description
This section provides an overview of the 1.8 Volt Intel Wireless Flash memory features, packaging,
signal naming, and device architecture.
2.1
Product Overview
The 1.8 Volt Intel Wireless Flash memory provides Read-While-Write (RWW) and Read-White-
Erase (RWE) capability with high-performance synchronous and asynchronous reads on package-
compatible densities with a 16-bit data bus. Individually-erasable memory blocks are optimally
sized for code and data storage. Eight 4-Kword parameter blocks are located in the parameter
partition at either the top or bottom of the memory map. The rest of the memory array is grouped
into 32-Kword main blocks.