參數(shù)資料
型號(hào)： GT-64010A
廠商： Galileo Technology Services, LLC
英文描述： System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器）
文件頁(yè)數(shù)： 101/111頁(yè)
文件大小： 671K
代理商： GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
9
Rev is io n 1. 1
Galileo
TechnologyTM
4. FUNCTIONAL DESCRIPTION
4.1
CPU Interface
The GT-64010A supports the R4XXX and R5000 family of 64-bit CPUs. It supports the IDT R4600, R4650, R4700, and
R5000 at up to 50MHz bus frequency. The GT-64010A has a 64 byte, 8 level deep, write buffer that can absorb up to
four CPU write transactions. Standard R4XXX write and the R4600 pipelined write modes are supported (the R4600 re-
issue option is not supported). CPU read requests are supported via two possible paths: reads from the PCI, and from
32-bit wide (or less) devices are performed through the GT-64010A; CPU reads from 64-bit devices bypass the GT-
64010A through an external latch that is controlled by the GT-64010A. The interface supports the big and little endian
options of the CPU.
4.2
Secondary Cache Support
The GT- 64010 supports the GT- 64012 secondary cache controller for the R4600/R4700 CPU’s. The Hit input pin
indicates to the GT-64010A if the current CPU read can be serviced from the cache memory or it needs to be serviced
by the GT-64010A. Flush and Invalidate operations on the secondary cache are ignored by the GT-64010A.
4.3
Address Space Decode
The GT-64010A uses a distributed address decoding scheme. Each “master” unit (CPU or PCI) has a separate
address decoding logic and registers. The DMA controller uses the address mapping of the CPU interface. Address
space for the different system resources is programmable and can be programmed differently in each “master” unit.
The system resources are divided into seven groups: RAS[1:0], RAS[3:2], CS[2:0], CS[3] & BootCS, Internal, PCI I/O,
and PCI memory. Each group can have a minimum of 2 Mbytes and a maximum of 256 Mbytes of address space. The
individual devices in the device groups (e.g. RAS[0]) are further sub decoded to 1 Mbyte resolution. The sub decoding
is not distributed in the different “master” units but is centralized in the Device Controller unit. The system resources
groups can be mapped into a 64 Gbyte address space for CPU accesses and into 4 Gbyte address space for the DMA
and PCI accesses.
When the CPU tries to access an address that is not supported, the GT-64010A will latch the address into the Bus
Error registers, and will issue a bus error (over SysCmd[5]) if the access was a read access, and an interrupt if it was a
read or write access.
DMAReq[0]*/
Ready*
I
DMA Request [0] / Ready: This pin has two functions: it serves as
a DMA request indication by an external device, or as a cycle
extender (when inactive during a device access, an access will
extend until Ready* is asserted). The function of this pin is program-
mable at reset.
JTAG
JTRST*
I
JTAG Reset: Asynchronous reset to test logic.
JTCLK
I
JTAG Clock: Clock for test logic. JTMS and JTDI are received on
the rising edge, JTDO is driven from the falling edge. This signal
determines the shifting rate.
JTMS
I
JTAG Mode Select: A broadcast signal which controls test logic
operation.
JTDI
I
JTAG Data In: Serial data input.
JTDO
O
JTAG Data Out: Serial data output. Tri-state changes on negative
change of JTCLK.
Pin Name
Type
Description
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