參數(shù)資料
型號(hào)： GT-64010A
廠(chǎng)商： Galileo Technology Services, LLC
英文描述： System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器）
文件頁(yè)數(shù)： 54/111頁(yè)
文件大?。?/td> 671K
代理商： GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
47
Rev is io n 1. 1
Galileo
TechnologyTM
H ead er Ty p e , L a t e n cy T i m er, C ach e L i n e , O f f set : 0x 00c
For more information on these fields, please refer to the PCI specification.
Access of PCI masters to DRAM banks, Devices and internal space is achieved once there is a match between the
address presented over the PCI bus and the space defined by the respective Base/Size register pair. The GT-64010A
incorporates three Swapped Base Address registers for RAS[1:0], RAS[3:2] and CS[3] & BootCS. When the address
matches a Swapped Base Address register (and of course should not match its respective non-Swap Base Address
register), the data transferred will undergo the opposite to what is indicated by the ByteSwap bit (bit[0] of 0xc00). e.g.
using this mechanism, one could write data directly to DRAM and read it byte-swapped without CPU processing.
The Size registers could not define a zero size space. In order to enable the system designer to use addresses which
are within a certain space without having the GT-64010A respond to these addresses, a Base Address Enable register
is incorporated. A disabled space will not trigger device response should the address fall within the space defined by its
Base/Size register pair.
R A S [ 1 : 0 ] Ba se A d d ress , O f f set : 0x010
R A S [ 1 : 0 ] S w ap p e d B ase A d d res s, O f f set : 0x028
R A S [ 3 : 2 ] Ba se A d d ress , O f f set : 0x014
R A S [ 3 : 2 ] S w ap p e d B ase A d d res s, O f f set : 0x02c
Bits
Field name
Function
Initial Value
7:0
CacheLine
Specifies the GT-64010A’s cache line size (size=8).
0x07
15:8
LatTimer
Specifies in units of PCI bus clocks the value of the
latency timer of the GT-64010A.
0x00
23:16
HeadType
Specifies the layout of bytes 10h through 3fh.
0x00
Bits
Field Name
Function
Initial Value
31:12
Base
Defines the address assignment of RAS[1:0] (see
RAS[1:0] Bank Size).
0x00000
Bits
Field Name
Function
Initial Value
31:12
Base
Defines the address assignment of Swapped
RAS[1:0] (see RAS[1:0] Bank Size).
0x00000
Bits
Field Name
Function
Initial Value
31:12
Base
Defines the address assignment of RAS[3:2] (see
RAS[3:2] Bank Size).
0x01000
Bits
Field Name
Function
Initial Value
31:12
Base
Defines the address assignment of swapped RAS[3:2]
(see RAS[3:2] Bank Size).
0x01000
相關(guān)PDF資料
PDF描述
GT-64012 Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000處理器的二級(jí)高速緩存控制器)
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
GT-96100A Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器)
GT5-2/1S-HU RECTANGULAR CONNECTOR
GT5-1S-HU(A) RECTANGULAR CONNECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GT64010A-B 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Peripheral IC
GT64010AB1 制造商:GALILEO 功能描述:*
GT64010A-P 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Peripheral IC
GT64011-A1-PBB-C000 制造商:Marvell 功能描述:
GT64115-A2-PBB-C000 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*