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參數(shù)資料
| 型號(hào)： | GT-64010A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器） |
| 文件頁數(shù)： | 58/111頁 |
| 文件大?。?/td> | 671K |
| 代理商： | GT-64010A |
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GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
50
R e v i s ion 1 . 1
Galileo
TechnologyTM
6. RESTRICTIONS
6.1
CPU Interface
a)
The CPU should not attempt an access before 10 TClk cycles following deassertion of Rst* have expired.
b)
CacheOpMap should not be written to a value other than 0 unless CachePres bit is set (see section 3.2).
c)
The CPU Interface supports only DDDD and DXDXDXDX write patterns.
d)
A PCI I/O read intended for synchronization barrier should not be more than one long word (4 bytes). Any PCI I/O
read of more than 4 bytes will be carried out without checking the internal FIFOs.
e)
A write of more than 4 bytes to internal space will be ignored. A read of more than 4 bytes to internal space will
result in transaction termination with bus-error indication (SysCmd[5] equal ‘1’).
6.2
Memory Interface
a)
If latches are not present, all banks must be programmed to be on the even bus. Programming the registers to 64-
bit mode or to dynamically controlled latches will result in an error.
b)
Unless the boot device is 64-bits wide, the boot will be on the even bank.
c)
All Device Parameters (section 3.7) must be greater or equal to 3. i.e., AccToFirst, AccToNext, ADSToWr, WrActive
and WrHigh.
d)
When working with an 8- or 16-bit bus from CPU, a read/write operation can not exceed 64-bits (8 bytes).
e)
When working with an 8- or 16-bit bus from DMA/PCI, a read/write operation can’t exceed 32-bits (4 bytes).
f)
When an erroneous address is issued or a burst operation is performed to an 8- or 16-bit device, the GT-64010A
forces an interrupt (unless masked). If a sequence of address misses occurs, there will be no other interrupt prior
to resetting the appropriate bit in the cause register and no new address will be registered in the Address Decode
Error register (0x470) prior to reading it.
g)
When the CPU reads from an address which is decoded in the CPU Interface Unit as being a hit for CS[2:0]* or
CS[4:3]* and decoded as a miss in the DRAM/Device Interface Unit, the cycle will complete only if Ready* is
asserted (i.e., driven low). Although being a result of improper and inconsistent programming of the address space
defining registers, the following 2 workarounds exist:
Ready* should always be asserted (low) when CSTiming* is inactive (high).
If the Ready* signal is not needed in the system, the DMAReq[0]/Ready* pin should either be programmed as
Ready* and constantly driven active (low) or be programmed as DMAReq[0]*.
6.3
PCI Interface
Note: No PCI access should be attempted before 6 PClk cycles following deassertion of Rst* have expired.
6.3.1. Master
a)
Latency count, as specified in LatTimer (section 3.14), should not be programmed to less than 6.
6.3.2. Slave
a)
The set bits in the Bank Size registers must be sequential.
b)
When the slave is locked, in order to prevent a deadlock, all transactions to internal registers (I/O or memory
cycles) are not supported (retry will be issued).
6.4
DMA
a)
Transfers of less than 4 bytes are not supported.
b)
In order to restart a channel after it has been enabled, it should first be checked that the DMAActSt bit is set to
NOT ACTIVE (see section 3.9).
c)
When Source or Destination address is decremented, both addresses should be word-aligned (that is, A1 and A0
should be both zero), and Byte Count should be a multiple of 4 (this applies for burst limits greater than 4 bytes).
d)
When burst limit is less than or equal to 4 bytes, no support in decrement.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64010A-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64010AB1 | 制造商:GALILEO 功能描述:* |
| GT64010A-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64011-A1-PBB-C000 | 制造商:Marvell 功能描述: |
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
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