參數(shù)資料
型號(hào): GT-64010A
廠商: Galileo Technology Services, LLC
英文描述: System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述: 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器(帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器)
文件頁(yè)數(shù): 33/111頁(yè)
文件大小: 671K
代理商: GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
28
R e v i s ion 1 . 1
Galileo
TechnologyTM
D evi ce B a n k0 P a ra met ers, O f f s et : 0x45c
D evi ce B a n k1 P a ra met ers, O f f s et : 0x460
Bits
Field name
Function
Initial Value
2:0
TurnOff
The number of cycles between the deassertion of
DevOE* (an externally extracted signal which is the
logical OR between CSTiming* and inverted DevRW*)
to a new AD bus cycle.
0x7
6:3
AccToFirst
The number of cycles in a read access from the
assertion of CS* to the cycle that the data will be
latched (by the external latches). Can be extended via
the Ready* pin.
0xf
10:7
AccToNext
The number of cycles in a read access from the cycle
that the first data was latched to the cycle that the
next data will be latched (in burst accesses). Can be
extended via the Ready* pin.
0xf
13:11
ADStoWr
The number of cycles from ADS* active to the asser-
tion of EWr* or OWr*.
0x7
16:14
WrActive
The number of cycles EWr* or OWr* are active. Can
be extended via the Ready* pin.
0x7
19:17
WrHigh
The number of cycles between deassertion and
assertion of EWr* or OWr*.
0x7
21:20
DevWidth
Device width.
00 - 8 bits
01- 16 bits
10- 32 bits
11 - 64 bits
0x2
22
Reserved
Read only.
0x1
23
DevLoc
32-bit, 16-bit, or 8-bit device location.
0 - Even bank
1 - Odd bank
0x0
24
Reserved
Read only.
0x0
25
LatchFunct
Latch function in read cycles.
0 - Always transparent
1 - Latch enable signals are active.
0x0
27:26
Reserved
Read only.
0x1
29:28
Reserved
Read only.
0x1
30
Parity
Parity support for the bank.
0- No parity support
1- Parity supported
0x0
Bits
Field Name
Function
Initial Value
30:0
Various
Fields function as in Device Bank0.
0x146fffff
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