參數(shù)資料
型號: GT-64010A
廠商: Galileo Technology Services, LLC
英文描述: System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述: 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器(帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器)
文件頁數(shù): 106/111頁
文件大?。?/td> 671K
代理商: GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
94
R e v i s ion 1 . 1
Galileo
TechnologyTM
5. Be careful if OEB is programmed at reset to have reverse polarity.
6. SysADC[3:0] from the CPU too, if parity is supported.
7. SysADC[7:4] from the CPU too, if partiy is supported.
8. Regardless of endianess,
ECAS[0]* always corresponds to SysAD[7:0] and AD[7:0].
ECAS[1]* always corresponds to SysAD[15:8] and AD[15:8].
ECAS[2]* always corresponds to SysAD[23:16] and AD[23:16].
ECAS[3]* always corresponds to SysAD[31:24] and AD[31:24].
OCAS[0]* always corresponds to SysAD[39:32] and AD[7:0].
OCAS[1]* always corresponds to SysAD[47:40] and AD[15:8].
OCAS[2]* always corresponds to SysAD[55:48] and AD[23:16].
OCAS[3]* always corresponds to SysAD[63:56] and AD[31:24].
10.2.2. 32-bit DRAM
It is the same for odd and even bank connections. It is optional to have one bidirectional buffer.
Notes:
1. Example shows even bank choice, but odd bank can be selected instead.
2. Regardless of endianess,
ECAS[0]* always corresponds to SysAD[7:0], SysAD[39:32] and AD[7:0].
ECAS[1]* always corresponds to SysAD[15:8], SysAD[47:40] and AD[15:8].
ECAS[2]* always corresponds to SysAD[23:16], SysAD[55:48] and AD[23:16].
ECAS[3]* always corresponds to SysAD[31:24], SysAD[63:56] and AD[31:24].
3. Be careful if OEB is programmed at reset to have reverse polarity.
4. Signals can be optionally buffered for load balancing.
Connection
Memory
Width
Connect...
To...
DRAM Address
4
32-bit
DAdr[11:0]
DRAM address pins
DRAM Data
(Latched)
1,2
32-bit
AD[31:0]
Even latch I/Os B side
‘0’
LEE
OEE*
OEB
3
Even latch I/Os A side
Even bank data pins
Even latch CLKAB and CLKBA
Even latch LEAB and LEBA
Even latch OEBA*
Even latch OEAB
DRAM Data
(No Latch)
1,2
32-bit
AD[31:0]
Even bank data pins
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