參數(shù)資料
型號(hào)： GT-64010A
廠商： Galileo Technology Services, LLC
英文描述： System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器）
文件頁(yè)數(shù)： 22/111頁(yè)
文件大?。?/td> 671K
代理商： GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
18
R e v i s ion 1 . 1
Galileo
TechnologyTM
5.2
CPU Interface
The CPU Interface Configuration register determines which of the different MIPS write protocols is supported, as well
as secondary cache issues and CPU endianess. The differences in protocol are minimal and they include support for
pipelined write, etc. The GT-64010A supports the Galileo GT-64012 secondary cache controller, and thus when the
CachePres bit is set to 1, the GT-64010A will not service cacheable read requests if there is a Hit indication from the
secondary cache. The CacheOpMap bits indicate which address bits will be used for cache flush and cache invalidate
operation by the GT-64012. When the GT-64010A finds a match between a ‘1’ in the read address and the CacheOp-
Map bits that are set to ‘1’, it will ignore the access, and the GT-64012 will flush or invalidate the secondary cache. For
example, setting bit 8 to ‘1’ indicates that SysAD[35] is connected to one of the two GT-64012’s TagOp inputs, setting
bit 7 to ‘1’ indicates that SysAD[34] is connected to one of them, etc.
Timer /Counter 3
0x85c
Timer /Counter Control
0x864
PCI Internal
Command
0xc00
Time Out & Retry
0xc04
RAS[1:0] Bank Size
0xc08
RAS[3:2] Bank Size
0xc0c
CS[2:0] Bank Size
0xc10
CS[3] & Boot CS Bank Size
0xc14
SErr Mask
0xc28
Interrupt Acknowledge
0xc34
Configuration Address
0xcf8
Configuration Data
0xcfc
Interrupts
Interrupt Cause
0xc18
CPU Mask
0xc1c
PCI Mask
0xc24
PCI Configuration
Device and Vendor ID
0x000
Status and Command
0x004
Class Code and Revision ID
0x008
Header Type, Latency Timer, Cache Line
0x00c
RAS[1:0] Base Address
0x010
RAS[1:0] Swapped Base Address
0x028
RAS[3:2] Base Address
0x014
RAS[3:2] Swapped Base Address
0x02c
CS[2:0] Base Address
0x018
CS[3] & Boot CS Base Address
0x01c
CS[3] & Boot CS Swapped Base Address
0x030
Internal Registers Memory Mapped Base Address
0x020
Internal Registers I/O Mapped Base Address
0x024
Base Address Registers’ Enable
0x034
Interrupt Pin and Line
0x03c
相關(guān)PDF資料
PDF描述
GT-64012 Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000處理器的二級(jí)高速緩存控制器)
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
GT-96100A Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器)
GT5-2/1S-HU RECTANGULAR CONNECTOR
GT5-1S-HU(A) RECTANGULAR CONNECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GT64010A-B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Peripheral IC
GT64010AB1 制造商:GALILEO 功能描述:*
GT64010A-P 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Peripheral IC
GT64011-A1-PBB-C000 制造商:Marvell 功能描述:
GT64115-A2-PBB-C000 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*