參數(shù)資料
型號(hào)： GT-64010A
廠商： Galileo Technology Services, LLC
英文描述： System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器）
文件頁(yè)數(shù)： 50/111頁(yè)
文件大?。?/td> 671K
代理商： GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
43
Rev is io n 1. 1
Galileo
TechnologyTM
I n t e r ru p t Ca u se, O f f set : 0x c18
Bits
Field Name
Function
Initial Value
0
IntSum
Interrupt summary. Logical OR of all the interrupt bits,
regardless of the Mask registers’ values.
0x0 Read only
1
MemOut
Asserts when the CPU accesses an address out of
range in the memory decoding or a burst access to 8-
/16-bit devices.
0x0
2
DMAOut
Asserts when the DMA accesses an address out of
range.
0x0
3
CPUOut
Asserts when the CPU accesses an address out of
range.
0x0
4
DMA0Comp
Asserts at completion of DMA Channel 0 transfer.
0x0
5
DMA1Comp
Asserts at completion of DMA Channel 1 transfer.
0x0
6
DMA2Comp
Asserts at completion of DMA Channel 2 transfer.
0x0
7
DMA3Comp
Asserts at completion of DMA Channel 3 transfer.
0x0
8
T0Exp
Asserts when Timer 0 expires.
0x0
9
T1Exp
Asserts when Timer 1 expires.
0x0
10
T2Exp
Asserts when Timer 2 expires.
0x0
11
T3Exp
Asserts when Timer 3 expires.
0x0
12
MasRdErr
Asserts when the GT-64010A detects a parity error
during a master read operation.
0x0
13
SlvWrErr
Asserts when the GT-64010A detects a parity error
during a slave write operation.
0x0
14
MasWrErr
Asserts when the GT-64010A detects a parity error
during a master write operation.
0x0
15
SlvRdErr
Asserts when the GT-64010A detects a parity error
during a slave read operation.
0x0
16
AddrErr
Asserts when the GT-64010A detects a parity error on
the address lines.
0x0
17
MemErr
Asserts when a memory parity error is detected.
Applicable only when an external parity checking
device is used.
0x0
18
MasAbort
Asserts upon master abort.
0x0
19
TarAbort
Asserts upon target abort.
0x0
20
RetryCtr
Asserts when the retry counter expires.
0x0
25:21
CPUInt
These bits are set by the CPU by writing ‘0’ to gener-
ate an interrupt on the PCI bus. They are cleared
when the PCI writes ‘0’.
0x0
29:26
PCIInt
These bits are set by the PCI by writing ‘0’ to generate
an interrupt on the CPU. They are cleared when the
CPU writes ‘0’.
0x0
30
CPUIntSum
Interrupt summary. Logical OR of bits[29:26,20:1],
masked by bits[29:26,20:1] of the CPU Mask register.
0x0
31
PCIIntSum
Interrupt summary. Logical OR of bits[25:1], masked
by bits[25:1] of the PCI Mask register.
0x0
All bits are cleared by writing a value of ‘0’ by the CPU or PCI, unless stated otherwise.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GT64010A-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
GT64010AB1 制造商:GALILEO 功能描述:*
GT64010A-P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
GT64011-A1-PBB-C000 制造商:Marvell 功能描述:
GT64115-A2-PBB-C000 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000
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