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參數(shù)資料
| 型號： | GT-64010A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器） |
| 文件頁數(shù)： | 27/111頁 |
| 文件大?。?/td> | 671K |
| 代理商： | GT-64010A |
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GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
22
R e v i s ion 1 . 1
Galileo
TechnologyTM
B u s E rr o r A d d r ess Hi g h P ro cesso r, Of f set : 0 x078
5.4
DRAM and Device Address Space
The Decode Address registers determine which physical device will be accessed when the CPU, DMA, or PCI issue an
address. The address decoding is done by comparing address bits 27:20 to be greater than or equal to the value in the
Low fields, and less than or equal to the value in the High fields. In case that no match occurs, an interrupt will be
issued and the address causing the error will be latched in the Address Decode Error register. This error can occur
when the CPU or PCI decoding matches the address while the sub-decoding done in the memory unit doesn’t match
any of the addresses defined in the address space.
R AS [ 0] L o w De co d e Ad d r ess, O f f s e t : 0 x400
R AS [ 0] H igh De code Ad dr ess, Of f set : 0 x404
R AS [ 1] L o w De co d e Ad d r ess, O f f s e t : 0 x408
R AS [ 1] H igh De code Ad dr ess, Of f set : 0 x40c
R AS [ 2] L o w De co d e Ad d r ess, O f f s e t : 0 x410
Bits
Field Name
Function
Initial Value
3:0
IlegHiAdd
This register captures bits 35:32 of an illegal 64-bit
address.
0x0
Bits
Field Name
Function
Initial Value
7:0
Low
DRAM bank 0 will be accessed when the decoded
addresses are between Low and High.
0x00
Bits
Field Name
Function
Initial Value
7:0
High
DRAM bank 0 will be accessed when the decoded
addresses are between Low and High.
0x07
Bits
Field Name
Function
Initial Value
7:0
Low
DRAM bank 1 will be accessed when the decoded
addresses are between Low and High.
0x08
Bits
Field Name
Function
Initial Value
7:0
High
DRAM bank 1 will be accessed when the decoded
addresses are between Low and High.
0x0f
Bits
Field Name
Function
Initial Value
7:0
Low
DRAM bank 2 will be accessed when the decoded
addresses are between Low and High.
0x10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64010A-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64010AB1 | 制造商:GALILEO 功能描述:* |
| GT64010A-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64011-A1-PBB-C000 | 制造商:Marvell 功能描述: |
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
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