參數(shù)資料
型號(hào)： GT-64010A
廠商： Galileo Technology Services, LLC
英文描述： System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器）
文件頁(yè)數(shù)： 48/111頁(yè)
文件大?。?/td> 671K
代理商： GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
41
Rev is io n 1. 1
Galileo
TechnologyTM
C S [ 3 ] a n d Bo o t C S B a n k S i z e , O f f s e t : 0xc14
S E r r M ask, Of f set : 0 xc28
I n t e r ru p t Ac k n o w l e d g e , O f f s et : 0xc34
Bits
Field Name
Function
Initial Value
31:12
BankSize
Specifies the CS[3] and Boot CS address mapping in
conjunction with the CS[3] and Boot CS Base Address
register.
Set to ‘0’ indicates that the corresponding bit in the
address and in the base address must be equal in
order to have a hit. Set to ‘1’ indicates that the corre-
sponding bit in the address is a don’t-care.
For example, bit 12 set to ‘1’ indicates that the CS[3]/
Boot CS size is 8KBytes (address bits [12:0] are
changeable/don’t-care). The set bits in the Bank Size
must be sequential (e.g. 000...001, 000...011,
000...111 are correct values, whereas 000...010 and
000...100 are not).
0x00fff
Bits
Field Name
Function
Initial Value
0
AddrErr
Mask bit. When set, SErr* is asserted when the GT-
64010A detects a parity error on the address lines.
0x0
1
MasWrErr
Mask bit. When set, SErr* is asserted when the GT-
64010A detects a parity error during a master write
operation.
0x0
2
MasRdErr
Mask bit. When set, SErr* is asserted when the GT-
64010A detects a parity error during a master read
operation.
0x0
3
MemErr
Mask bit. When set, SErr* is asserted when a memory
parity error has been detected (applicable only when
an external parity checking device is used).
0x0
4
MasAbort
Mask bit. When set, SErr* is asserted when the GT-
64010A performs master abort.
0x0
5
TarAbort
Mask bit. When set, SErr* is asserted when the GT-
64010A detects a target abort.
0x0
Bits
Field Name
Function
Initial Value
31:0
IntAck
The data is meaningless. A CPU read operation to
this register causes the GT-64010A to perform an
Interrupt Acknowledge cycle on the PCI bus.
0x00000000
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