HITACHI 215
Table 10.1
ITU Functions
Item
Counter clocks
Channel 0
Internal:
φ
,
φ
/2,
φ
/4,
φ
/8
External: Independently selectable from TCLKA, TCLKB, TCLKC, and TCLKD
GRA0, GRB0
GRA1, GRB1
GRA2, GRB2
Channel 1
Channel 2
Channel 3
Channel 4
General registers
(output compare/
input capture dual
registers)
Buffer registers
Input/output pins
GRA3, GRB3
GRA4, GRB4
No
TIOCA0,
TIOCB0
No
No
TIOCA1,
TIOCB1
No
No
TIOCA2,
TIOCB2
No
BRA3, BRB3
TIOCA3,
TIOCB3
No
BRA4, BRB4
TIOCA4,
TIOCB4
TOCXA4,
TOCXB4
GRA4/GRB4
Output pins
Counter clear func-
tion (compare mat-
ch or input capture)
Compare 0
match
output
GRA0/GRB0
GRA1/GRB1
GRA2/GRB2
GRA3/GRB3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
1
Toggle
output
Input capture
function
Synchronization
PWM mode
Reset-synchronized
PWM mode
Complementary
PWM mode
Phase counting
mode
Buffer operation
DMAC activation
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
No
No
Yes
No
No
No
GRA0 com-
pare match or
input capture
Compare
match/input
capture A0
Compare
match/input
capture B0
Overflow
No
GRA1 com-
pare match or
input capture
Compare
match/input
capture A1
Compare
match/input
capture B1
Overflow
No
GRA2 com-
pare match or
input capture
Compare
match/input
capture A2
Compare
match/input
capture B2
Overflow
Yes
GRA3 com-
pare match or
input capture
Compare
match/input
capture A3
Compare
match/input
capture B3
Overflow
Yes
No
Interrupt sources
(three)
Compare
match/input
capture A4
Compare
match/input
capture B4
Overflow