HITACHI 458
Table 19.7
Bus Timing (2)
Conditions: V
CC
= 5.0 V ±10%, V
SS
= 0 V,
φ
= 16.6 MHz, Ta = –20 to +75°C*
*: Normal products. Ta = –40 to +85°C for wide-temperature range products.
Item
Address delay time
Symbol
t
AD
Min
—
Max
25
*1
Unit
ns
Figures
19.8, 19.9, 19.11–19.14,
19.19, 19.20
19.8, 19.9, 19.20
CS
delay time 1
CS
delay time 2
CS
delay time 3
CS
delay time 4
Access time 1
*6
from read strobe
t
CSD1
t
CSD2
t
CSD3
t
CSD4
t
RDAC1
—
—
—
—
t
cyc
×
0.65 –
20
t
cyc
×
0.5 –
20
t
cyc
×
(n +
1.65) – 20
*3
t
cyc
×
(n +
1.5) – 20
*3
t
cyc
×
(n +
0.65) – 20
*3
t
cyc
×
(n +
0.5) – 20
*3
—
15
0
—
30
25
25
25
—
ns
ns
ns
ns
ns
19.19
35% duty
*2
19.8
50% duty
—
ns
Access time 2
*6
from read strobe
35% duty
*2
t
RDAC2
—
ns
19.9, 19.10
50% duty
—
ns
Access time 3
*6
from read strobe
35% duty
*1
t
RDAC3
—
ns
19.19
50% duty
—
ns
Read strobe delay time
Read data setup time
Read data hold time
Write strobe delay time 1
t
RSD
t
RDS
t
RDH
t
WSD1
25
—
—
25
ns
ns
ns
ns
19.8, 19.9, 19.19
19.8, 19.9, 19.11–19.14,
19.19
19.9, 19.13, 19.14, 19.19,
19.20
19.9, 19.13, 19.14, 19.19
19.11, 19.12
19.11, 19.12, 19.20
19.9, 19.13, 19.14, 19.19
19.11, 19.12
19.9, 19.11–19.14
19.9, 19.13, 19.14
19.11, 19.12
19.9, 19.11–19.14
Write strobe delay time 2
Write strobe delay time 3
Write strobe delay time 4
Write data delay time 1
Write data delay time 2
Write data hold time
Parity output delay time 1
Parity output delay time 2
Parity output hold time
t
WSD2
t
WSD3
t
WSD4
t
WDD1
t
WDD2
t
WDH
t
WPDD1
t
WPDD2
t
WPDH
—
—
—
—
—
0
—
—
0
25
25
25
45
25
—
45
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns