HITACHI 474
Table 19.8
Bus Timing (3)
Conditions: V
CC
= 3.0 to 5.5 V, V
SS
= 0 V,
φ
= 12.5 MHz, Ta = –20 to +75°C*
*: Normal products. Ta = –40 to +85°C for wide-temperature range products.
Item
Symbol Min
Max
Unit
Figures
Address delay time
t
AD
—
40
ns
19.21, 19.22, 19.24–
19.27, 19.32, 19.33
CS
delay time 1
CS
delay time 2
CS
delay time 3
CS
delay time 4
Access time 1
*4
from read strobe50% duty
Access time 2
*4
from read strobe50% duty
Access time 3
*4
from read strobe50% duty
t
CSD1
t
CSD2
t
CSD3
t
CSD4
—
40
ns
19.21, 19.22, 19.33
—
40
ns
—
40
ns
19.32
—
40
ns
35% duty
*1
t
RDAC1
t
cyc
×
0.65 – 35
t
cyc
×
0.5 – 35
t
cyc
×
(n+1.65) – 35
*2
—
t
cyc
×
(n+1.5) – 35
*2
t
cyc
×
(n+0.65) – 35
*2
—
t
cyc
×
(n+0.5) – 35
*2
—
—
ns
19.21,
—
ns
35% duty
*1
t
RDAC2
ns
19.22, 19.23
—
ns
35% duty
*1
t
RDAC3
ns
19.32
—
ns
Read strobe delay time
t
RSD
t
RDS
t
RDH
t
WSD1
40
ns
19.21, 19.22, 19.32
Read data set-up time
30
—
ns
19.21, 19.22,
Read data hold time
0
—
ns
19.24-19.27, 19.32
Write strobe delay time 1
—
40
ns
19.22, 19.26, 19.27,
19.32, 19.33
Write strobe delay time 2
t
WSD2
—
30
ns
19.22, 19.26, 19.27,
19.32
Write strobe delay time 3
t
WSD3
t
WSD4
t
WDD1
—
40
ns
19.24, 19.25
Write strobe delay time 4
—
40
ns
19.24, 19.25, 19.33
Write data delay time 1
—
70
ns
19.22, 19.26, 19.27,
19.32
Write data delay time 2
t
WDD2
t
WDH
—
40
ns
19.24, 19.25
Write data hold time
–10
—
ns
19.22, 19.24–19.27,
19.32
Parity output delay time 1
t
WPDD1
t
WPDD2
t
WPDH
—
80
ns
19.22, 19.24, 19.27
Parity output delay time 2
—
40
ns
19.24, 19.25
Parity output hold time
–10
—
ns
19.22, 19.24–19.27