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參數(shù)資料
| 型號： | HSP3824VI |
| 廠商： | Harris Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | 直接序列擴頻基帶處理器 |
| 文件頁數(shù)： | 16/41頁 |
| 文件大?。?/td> | 276K |
| 代理商： | HSP3824VI |
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16
HSP3824
when it needs to de-assert the MD_RDY interface signal.
MD_RDY envelopes the received data packet as it is being
output to the external processor.
CCITT - CRC 16 Field (16 Bits) -
This field includes the 16-
bit CCITT - CRC 16 calculation of the five header fields. This
value is compared with the CCITT - CRC 16 code calculated
at the receiver. The HSP3824 receiver can be programmed
to drop the link upon a CCITT - CRC 16 error or it can be
programmed to ignore the error and to continue with data
demodulation.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones compliment of
the remainder generated by the modulo 2 division of the pro-
tected bits by the polynominal:
X
16
+ x
12
+ x
5
+ 1
The protected bits are processed in transmit order. All CRC
calculations are made prior to data scrambling. A shift regis-
ter with two taps is used for the calculation. It is preset to all
ones and then the protected fields are shifted through the
register. The output is then complimented and the residual
shifted out MSB first.
When the HSP3824 generates the preamble and header inter-
nally it can be configured into one of four link protocol modes.
Mode 0 -
In this mode the preamble is programmable up to 256
bits (all 1's) and the SFD field is the only field utilized for the
header. This mode only supports DBPSK transmissions for the
entire packet (preamble/header and data).
Mode 1 -
In this mode the preamble is programmable up to 256
bits (all 1's) and the SFD and CCITT - CRC 16 fields are used
for the header. The data that follows the header can be either
DBPSK or DQPSK. The receiver and transmitter must be pro-
grammed to the proper modulation type.
Mode 2 -
In this mode the preamble is programmable up to 256
bits (all 1's) and the SFD, Length Field, and CCITT - CRC 16
fields are used for the header. The data that follows the header
can be either DBPSK or DQPSK. The receiver and transmitter
must be programmed to the proper modulation type.
Mode 3 -
In this mode the preamble is programmable up to
256 bits (all 1's). The header in this mode is using all available
fields. In mode 3 the signal field defines the modulation type of
the data packet (DBPSK or DQPSK) so the receiver does not
need to be preprogrammed to anticipate one or the other. In
this mode the device checks the Signal field for the data
packet modulation and it switches to DQPSK if it is defined as
such in the signal field. Note that the preamble and header
are always DBPSK the modulation definition applies only for
the data packet. This mode is called the full protocol mode in
this document.
Figure 10 summarizes the four preamble/head or modes. In the
case that the device is configured to accept the preamble and
header from an external source it still needs to be configured in
one of the four modes (0:3). Even though the HSP3824 trans-
mitter does not generate the preamble and header information
the receiver needs to know the mode in use so it can proceed
with the proper protocol and demodulation decisions.
The following Configuration Registers (CR)are used to program
the preamble/header functions, more programming details
about these registers can be found in the Control Registers
section of this document:
CR 0 -
Defines one of the four modes (bits 4, 3) for the TX.
Defines whether the SFD timer is active (bit 2). Defines whether
the receiver should stop demodulating after the number of sym-
bols indicated in the Length field has been met.
CR 2 -
Defines to the receiver one of the four protocol modes
(bits 1, 0). Indicates whether any detected CCITT - CRC 16
errors need to reset the receiver (return to acquisition) or to
ignore them and continue with demodulation (bit 5). Specifies a
128-bit preamble or an 80-bit preamble (bit 2).
CR 3 -
Defines internal or external preamble generation (bit 2).
Indicates to the receiver the data packet modulation (bit 0), note
that in mode 3 the contents of this register are overwritten by
the information in the received signal field of the header. CR 3
specifies the data modulation type used to the transmitter (bit
1). Bit 1 defines the contents of the signaling field in the header
to indicate either DBPSK or DQPSK modulation.
CR 41 -
Defines the length of time that the demodulator
searches for the SFD before returning to acquisition.
CR 42 -
The contents of this register indicate that the transmit-
ted data is DBPSK. If CR 4-bit 1 is set to indicate DBPSK mod-
ulation then the contents of this register are transmitted in the
signal field of the header.
CR 43 -
The contents of this register indicates that the transmit-
ted data is DQPSK. If CR 4-bit 1 is set to indicate DQPSK mod-
ulation then the contents of this register are transmitted in the
signal field of the header.
CR 44, 45, 46, 47, 48 -
Status, read only, registers that indicate
the service field, data length field and CCITT - CRC 16 field val-
ues of the received header.
CR 49, 50 -
Defines the transmit SFD field value of the header.
The receiver will always search to detect this value before it
declares a valid data packet.
CR 51 -
Defines the contents of the transmit service field.
CR 52, 53 -
Defines the value of the transmit data length field.
This value includes all symbols following the last header field
symbol.
CR 54,55 -
Status, read only, registers indicating the calculated
CCITT - CRC 16 value of the most recently transmitted header.
CR 56 -
Defines the number of preamble synchronization bits
that need to be transmitted when the preamble is internally
generated. These symbols are used by the receiver for initial
PN acquisition and they are followed by the header fields.
The full protocol requires a setting of 128d = 80h. For other
applications, in general increasing the preamble length will
improve low signal to noise acquisition performance at the cost
of greater link overhead. For dual receive antenna operation,
the minimum suggested value is 128d = 80h. For single receive
antenna operation, the minimum suggested value is 80d = 50h.
These suggested values include a 2 symbol TX power amplifier
ramp up. If an AGC is used, its worst case settling time in sym-
bols should be added to these values.
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