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參數(shù)資料
| 型號： | HSP3824VI |
| 廠商： | Harris Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | 直接序列擴(kuò)頻基帶處理器 |
| 文件頁數(shù)： | 37/41頁 |
| 文件大?。?/td> | 276K |
| 代理商： | HSP3824VI |
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37
Specifications HSP3824 at 33MHz
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to V
CC
+0.5V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Lead Temperature (Soldering 10s) (Lead Tips Only) . . . . . . +300
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance (Typical)
TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Power Dissipation at 85
o
C
TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.81W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25,000 Gates
θ
JA
80
ο
C/W
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +2.70V to +5.50V
Operating Temperature Range . . . . . . . . . . . . . . . . .-40
o
C to +85
o
C
DC Electrical Specifications
V
CC
= 3.0V to 5.0V
±
10%, T
A
= -40
o
to +85
o
C
PARAMETER
SYMBOL
I
CCOP
TEST CONDITIONS
MIN
-
TYP
69
MAX
77
UNITS
mA
Power Supply Current
V
CC
= Max, CLK Frequency 22MHz
(Notes 1, 2)
V
CC
= Max, Outputs Not Loaded
V
CC
= Max, Input = 0V or V
CC
V
CC
= Max, Input = 0V or V
CC
V
CC
= Max, Min
V
CC
= Min, Max
I
OH
= -1mA, V
CC
= Min
I
OL
= 2mA, V
CC
= Min
CLK Frequency 1MHz
All measurements referenced to GND.
T
A
= +25
o
C, Note 2
Standby Power Supply Current
Input Leakage Current
Output Leakage Current
Logical One Input Voltage
Logical Zero Input Voltage
Logical One Output Voltage
Logical Zero Output Voltage
Input Capacitance
Output Capacitance
I
CCSB
I
I
I
O
V
IH
V
IL
V
OH
V
OL
C
IN
C
OUT
-
1
1
1
2.5
10
10
-
V
CC
/3
-
0.4
10
10
mA
μ
A
μ
A
V
V
V
V
pF
pF
-10
-10
0.7 V
CC
-
V
CC
-0.4
-
-
-
V
CC
-.2
.2
5
5
NOTES:
1. Output load 30pF. I
CCOP
= 5.5 + 4.7(V) + 3.7E - 7 (V)(f); V = Volts, f = Freq. Example: 5.5 + 4.7(5.5) + 3.7E - 7(5.5)(22E6) = 77
2. Not tested, but characterized at initial design and at major process/design changes.
AC Electrical Specifications
V
CC
= 3.0V to 5.0V
±
10%, T
A
= -40
o
to +85
o
, (Note 1)
PARAMETER
SYMBOL
t
CP
t
CH
t
CL
t
S2
t
H2
t
P
t
H
t
L
t
S1
t
H1
t
D1
t
E1
t
F1
t
D2
t
D3
t
D4
-
33MHz
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns (Note 2)
ns (Note2)
ns
ns
ns
-
ns (Note 2, 3)
MIN
30
9
9
10
20
MAX
-
-
-
-
-
-
-
-
-
-
30
20
20
35
35
40
-
10
CLK Period (MCLK)
CLK High (MCLK)
CLK Low (MCLK)
Setup Time to MCLK (TXD)
Hold Time from MCLK (TXD)
SCLK Clock Period
SCLK High
SCLK Low
Set up to SCLK (SD, AS, R/W, CS)
Hold Time from SCLK (SD, AS, R/W, CS)
SD
OUT
from SCLK
Output Enable of Sd from R/W High
Output disable of SD after R/W Low
TXCLK, TXRDY, I, Q from MCLK
RXCLK, MD_RDY, RXD from MCLK
TEST 0-7, CCA, AGC, from MCLK
ANSTEL, TEST_CK
OUTPUT Rise/Fall
NOTES:
1. AC tests performed with C
L
= 40pF, I
OL
= 2mA, and I
OH
= -1mA. Input reference level all inputs 1.5V. Test V
IH
= V
CC
, V
IL
= 0V; V
OH
= V
OL
= V
CC
/2.
2. Not tested, but characterized at initial design and at major process/design changes.
3. Measured from V
IL
to V
IH
.
100ns or MCLK
20
20
20
20
-
-
-
-
-
-
-
-
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