參數(shù)資料
型號(hào)： HSP3824VI
廠商： Harris Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor
中文描述： 直接序列擴(kuò)頻基帶處理器
文件頁(yè)數(shù)： 27/41頁(yè)
文件大?。?/td> 276K
代理商： HSP3824VI
27
HSP3824
Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
CONFIGURATION REGISTER 0 ADDRESS (0h) MODEM CONFIGURATION REGISTER A
Bit 7
This bit selects the transmit antenna, controlling the output ANT_SEL pin. It is only used in half duplex mode. (Bit 5 = 0)
Logic 1 = Antenna A.
Logic 0 = Antenna B.
Bit 6
In single antenna operation this bit is used as the output of the ANT_SEL pin. In dual antenna mode this bit is ignored.
Logic 1 = Antenna A.
Logic 0 = Antenna B.
Bit 5
This control bit is used to select between full duplex and half duplex operation. If set for full duplex operation, the
ANT_SEL pin reflects the setting of CR0 bit 7 when TX_PE is active and reflects the receiver’s choice when TX_PE is
inactive. In full duplex operation, the ANT_SEL pin always reflects the receiver’s choice antenna.
Logic 1 = full duplex.
Logic 0 = half duplex.
Bit 4, 3
These control bits are used to select one of the four input Preamble Header modes for transmitting data. The preamble
and header are DBPSK for all modes of operation. Mode 0 is followed by DBPSK data. For modes 1-3, the data can
be configured as either DBPSK or DQPSK. This is a “don’t care” if the header is generated externally.
Bit 2
This control bit is used to enable the SFD (Start Frame Delimiter) timer. If the time is set and expires before the SFD
has been detected, the HSP3824 will return to its acquisition mode.
Logic 1: Enables the SFD timer to start counting once the PN acquisition has been achieved.
Logic 0: Disables the SFD Timer.
Bit 1
This control bit enables counting the number of data bits per the length field embedded in the header. Only used in
header modes 2 and 3. Then according to the count it returns the processor into its acquisition mode at the end of the
count. If length field is 0000h, modem will reset at end of SFD regardless of this bit setting.
Logic 1 = Enable Length Time Out.
Logic 0 = Disabled.
Bit 0
Unused don’t care.
CONFIGURATION REGISTER 1 ADDRESS (04h) MODEM CONFIGURATION REGISTER B
Bit 7
When active this bit maintains the RXCLK and TXLK rates constant for preamble and data transfers even if the data
is modulated in DQPSK. This bit is used if the external processor can not accommodate rate changes. This is an active
high signal. The rate used is the QPSK rate and the BPSK header bits are double clocked.
Bit 6, 5, 4, 3, 2
These control bits are used to define a binary count (N) from 0 - 31. This count is used to assert TX_RDY N - clocks
(TXCLK) before the beginning of the first data bit. If this is set to zero, then the TX_RDY will be asserted immediately
after the last bit of the Preamble Header.
Bit 1
When active the internal A/D calibration circuit sets the reference to mid-scale. When inactive then the calibration cir-
cuit adjusts the reference voltage in real time to optimize I, Q levels.
Logic 1 = Reference set at mid-scale (fixed).
Logic 0 = Real time reference adjustment.
Bit 0
When active the A/D calibration circuit is held at its last value.
Logic 1 = Reference held at the most recent value.
Logic 0 = Real time reference level adjustment.
MODE
BIT 4
BIT 3
MODE DESCRIPTION
0
0
0
Preamble with SFD Field.
1
0
1
Preamble with SFD, and CRC16.
2
1
0
Preamble with SFD, Length, and CRC16.
3
1
1
Full preamble and header.
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