參數資料
型號： HSP3824VI
廠商： Harris Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor
中文描述： 直接序列擴頻基帶處理器
文件頁數： 24/41頁
文件大?。?/td> 276K
代理商： HSP3824VI
24
HSP3824
FIGURE 18. BER vs EB/N0 PERFORMANCE
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data
clock offsets of up to
±
25ppm for each end of the link (TX
and RX). This effects both the acquisition and the tracking
performance of the demodulator. The budget for clock offset
error is 0.75dB at
±
50ppm as shown in Figure 19.
OFFSET IN ppm
FIGURE 19. BER vs CLOCK OFFSET
Carrier Offset Frequency Performance
The correlators in the baseband processor are time invariant
matched filter correlators otherwise known as parallel corre-
lators. They use two samples per chip and are tapped at
every other shift register stage. Their performance with car-
rier frequency offsets is determined by the phase roll rate
due to the offset. For an offset of +50ppm (combined for both
TX and RX) will cause the carrier to phase roll 22.5 degrees
over the length of the correlator. This causes a loss of
0.22dB in correlation magnitude which translates directly to
Eb/N0 performance loss. In the PRISM chip design, the corr-
elator is not included in the carrier phase locked loop correc-
tion, so this loss occurs for both acquisition and data. Figure
20 shows the loss versus carrier offset taken out to +350kHz
(120kHz is 50ppm at 2.4GHz).
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1
1
1
1
1
1
9
8
Eb/N0 IN dB
B
THEORY (DBPSK)
DBPSK
DQPSK
1E-5
1E-4
1E-3
-100
-60
-20
20
60
100
B
FIGURE 20. BER vs CARRIER OFFSET
I/Q Amplitude Imbalance
Imbalances in the signal cause differing effects depending
on where they occur. In a system using a limiter, if the imbal-
ances are in the transmitter, that is, before the limiter, ampli-
tude imbalances translate into phase imbalances between
the I and Q symbols. If they occur in the receiver after the
limiter, they are not converted to phase imbalances in the
symbols, but into vector phase imbalances on the composite
signal plus noise. The following curve shows data taken with
amplitude imbalances in the transmitter. Starting at the bal-
anced condition, I = 100% of Q, the bit error rate degrades
by two orders of magnitude for a 3dB drop in I (70%).
FIGURE 21. I/Q IMBALANCE EFFECTS
A Default Register Configuration
The registers in the HSP3824 are addressed with 14-bit num-
bers where the lower 2 bits of a 16-bit hexadecimal address
are left as unused. This results in the addresses being in
increments of 4 as shown in the table below. Table 10 shows
the register values for a default Full Protocol configuration
(Mode 3) with a single antenna. The data is transmitted as
DQPSK. This is a recommended configuration for initial test
and verification of the device and /or the radio design. The
user can later modify the CR contents to reflect the system
and the required performance of each specific application.
1E-6
1E-5
1E-4
1E-3
-
-
-
-
5
1
2
3
FREQUENCY OFFSET (kHz)
B
1E-05
1E-04
1E-03
1E-02
1E-01
1
9
8
8
7
7
PERCENT AMPLITUDE BALANCE
8
B
9
6
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