- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370702 > HSP3824VI (Harris Corporation) Direct Sequence Spread Spectrum Baseband Processor PDF資料下載
參數(shù)資料
| 型號： | HSP3824VI |
| 廠商： | Harris Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | 直接序列擴頻基帶處理器 |
| 文件頁數(shù)： | 33/41頁 |
| 文件大小： | 276K |
| 代理商： | HSP3824VI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
33
HSP3824
CONFIGURATION REGISTER 19 ADDRESS (4Ch) RSSI THRESHOLD, ENERGY DETECT
Bits 0 - 7
This register contains the value for the RSSI threshold for measuring and generating energy detect (ED). When the
RSSI exceeds the threshold ED is declared. ED indicates the presence of energy in the channel. The threshold that
activates ED is programmable. Bits 7 an 6 of this register are not used and set to Logic 0.
CONFIGURATION REGISTER 20 ADDRESS (50h) RX SPREAD SEQUENCE (HIGH)
Bits 0 - 7
This 8-bit register is programmed with the upper byte of the receive despreading code. This code is used for both the
I and Q signalling paths of the receiver. This register combined with the lower byte RX_SPRED(LOW) generates a
receive despreading code programmable up to 16 bits. Right justified MSB first. See address 13 and 14 for example.
CONFIGURATION REGISTER 21 ADDRESS (54h) RX SPREAD SEQUENCE (LOW)
Bits 0 - 7
This 8-bit register is programmed with the lower byte of the receiver despreading code. This code is used for both the
I and Q signalling paths of the receiver. This register combined with the upper byte RX_SPRED(HIGH) generates a
receive despreading code programmable up to 16 bits.
CONFIGURATION REGISTER 22 ADDRESS (58h) RX SIGNAL QUALITY 1 ACQ (HIGH) THRESHOLD
Bits 0 - 7
This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for
acquisition. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude
signal quality measurements made during acquisition at each antenna dwell. This threshold comparison is added with
the SQ2 threshold in registers 30 and 31 for acquisition. A lower value on this threshold will increase the probability of
detection and the probability of false alarm. Set the threshold according to instructions in the text.
CONFIGURATION REGISTER 23 ADDRESS (5Ch) RX SIGNAL QUALITY 1 ACQ THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for ac-
quisition. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude sig-
nal quality measurement made during acquisition at each antenna dwell.
CONFIGURATION REGISTER 24 ADDRESS (60h) RX SIGNAL QUALITY 1 ACQ READ (HIGH)
Bits 0 - 7
This status register contains the upper byte bits (8 - 14) of the measured signal quality threshold for the bit sync am-
plitude used for acquisition. This register combined with the lower byte represents a 15-bit value, representing the mea-
sured bit sync amplitude. This measurement is made at each antenna dwell and is the result of the best antenna.
CONFIGURATION REGISTER 25 ADDRESS (64h) RX SIGNAL QUALITY 1 ACQ READ (LOW)
Bits 0 - 7
This register contains the lower byte bits (0 - 7) of the measured signal quality threshold for the bit sync amplitude used
for acquisition. This register combined with the higher byte represents a 15-bit value, of the measured bit sync ampli-
tude. This measurement is made at each antenna dwell and is the result of the best antenna.
CONFIGURATION REGISTER 26 ADDRESS (68h) RX SIGNAL QUALITY 1 DATA THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8-14) of the bit sync amplitude signal quality threshold used for drop
lock decisions. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude
signal quality measurements, made every 128 symbols. These thresholds set the drop lock probability. A higher value
will increase the probability of dropping lock.
CONFIGURATION REGISTER ADDRESS 27 (6Ch) RX SIGNAL QUALITY 1 DATA THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for drop
lock decisions. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude
signal quality measurements, made every 128 symbols.
MSB
LSB
Bits (0:7)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
00h (Min)
RSSI_STAT
0 0 1 1 1 1 1 1
3Fh (Max)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSR101 | Silicon Schottky Barrier Diode for Various detector, High speed switching(用于多種檢波和高速開關(guān)的肖特基勢壘二極管) |
| HSRD1056RH165S | Converter IC |
| HSRD1056RH169H | Converter IC |
| HSRD1056RH169S | Converter IC |
| HSRD1056RH240H | Converter IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP3824VI96S5001 | 制造商:Harris Corporation 功能描述: |
| HSP40223221 | 制造商:PARMAR 功能描述:BALLAST HPS/MH 400W 制造商:PARMAR 功能描述:BALLAST, HPS/MH, 400W |
| HSP4070C | 制造商:JLWORLD 制造商全稱:JLWORLD 功能描述:SPEAKER SOUND GENERATORS |
| HSP40G-8 | 制造商:JLWORLD 制造商全稱:JLWORLD 功能描述:SPEAKER SOUND GENERATORS |
| HSP43124 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Serial I/O Filter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。