參數(shù)資料
型號: HSP3824VI
廠商: Harris Corporation
元件分類: 基帶處理器
英文描述: Direct Sequence Spread Spectrum Baseband Processor
中文描述: 直接序列擴(kuò)頻基帶處理器
文件頁數(shù): 36/41頁
文件大小: 276K
代理商: HSP3824VI
36
HSP3824
CONFIGURATION REGISTER 49 ADDRESS (C4h) SFD (HIGH)
Bits 0 - 7
This 8-bit register contains the upper byte bits (8-15) of the SFD used for both the Transmit and Receive header. This
register combined with the lower byte represents the 16-bit value for the SFD field.
CONFIGURATION REGISTER 50 ADDRESS (C8h) SFD (LOW)
Bits 0 - 7
This 8-bit register contains the upper byte bits (0-7) of the SFD used for both the Transmit and Receive header. This
register combined with the lower byte represents the 16-bit value for the SFD field.
CONFIGURATION REGISTER 51 ADDRESS (CCh) TX SERVICE FIELD
Bits 0 - 7
This 8-bit register is programmed with the 8-bit value of the Service Field to be transmitted in a Header. This field is
reserved for future use and should be always a 00h.
CONFIGURATION REGISTER 52 ADDRESS (D0h) TX DATA LENGTH FIELD (HIGH)
Bits 0 - 7
This 8-bit register contains the higher byte (bits 8-15) of the transmit Length Field described in the Header. This byte
combined with the lower byte indicates the number of bits to be transmitted in the data packet. CR 52/53 should not
be set to 0000h. This value would cause the modem to reset after SFD.
CONFIGURATION REGISTER 53 ADDRESS (D4h) TX DATA LENGTH FIELD (LOW)
Bits 0 - 7
This 8-bit register contains the lower byte bits (0-7) of the transmit Length Field described in the Header. This byte
combined with the higher byte indicates the number of bits to be transmitted in the data packet, including the MAC
payload header. CR 52/53 should not be set to 0000h. This value would cause the modem to reset after SFD.
CONFIGURATION REGISTER 54 ADDRESS (D8h) TX CRC16 (HIGH)
Bits 0 - 7
This 8-bit register contains the upper byte (bits 8-15) of the transmitted CRC16 Field for the Header. This register
combined with the lower byte represents a 16-bit CRC16 value calculated by the HSP3824 to protect the transmitted
header. The fields protected are selected by configuring the header mode control bits at register address 02.
CONFIGURATION REGISTER 55 ADDRESS (DCh) TX CRC16 (LOW)
Bits 0 - 7
This 8-bit register contains the lower byte (bits 0-7) of the transmitted CRC16 Field for the Header. This register com-
bined with the higher byte represents a 16-bit CRC16 value calculated by the HSP3824 to protect the transmitted
header. The fields protected are selected by configuring the header mode control bits at register address 02.
configuration register 2
CONFIGURATION REGISTER 56 ADDRESS (E0h) TX PREAMBLE LENGTH
Bits 0 - 7
This register contains the count for the Preamble length counter. This counter is programmable up to 8 bits and rep-
resents the number of preamble bits. This should be set at 50h for 1 antenna and 80h for dual antennas.
MSB
LSB
RX_CRC16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_CRC16(HIGH)
7 6 5 4 3 2 1 0
RX_CRC16(LOW)
7 6 5 4 3 2 1 0
NOTE: The receive CRC16 Field protects the following fields depending
upon the mode selection. as defined in register address 02.
Mode 0 CRC16 not used
Mode 1 CRC16 protects SFD
Mode 2 CRC16 protects SFD, and Length Field
Mode 3 CRC16 protects Signalling Field, Service Field, and Length Field
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