參數(shù)資料
型號(hào)： HSP3824VI
廠商： Harris Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor
中文描述： 直接序列擴(kuò)頻基帶處理器
文件頁數(shù)： 35/41頁
文件大?。?/td> 276K
代理商： HSP3824VI
35
HSP3824
CONFIGURATION REGISTER 39 ADDRESS RESERVED
Reserved
CONFIGURATION REGISTER 40 ADDRESS RESERVED
Reserved
CONFIGURATION REGISTER 41 ADDRESS (A4h) SFD SEARCH TIME
Bits 0 - 7
This register is programmed with an 8-bit value which represents the length of time for the demodulator to search for
a SFD in a receive Header. Each bit increment represents 1 symbol period.
CONFIGURATION REGISTER 42 ADDRESS (A8h) DSBPSK SIGNAL
Bits 0 - 7
This register contains an 8-bit value indicating the data packet modulation is DBPSK. This value will be a OAH for full
protocol operation at a data rate of 1 MBPS, and is used in the transmitted Signalling Field of the header. This value
will also be used for detecting the modulation type on the received Header.
CONFIGURATION REGISTER 43 ADDRESS (ACh) DQPSK SIGNAL
Bits 0 - 7
This register contains the 8-bit value indicating the data packet modulation is DQPSK. This value will be a 14h for full
protocol operation at a data rate of 2 MBPS and is used in the transmitted Signalling Field of the header. This value
will also be used for detecting the modulation type on the received header.
CONFIGURATION REGISTER 44 ADDRESS (B0h) RX SERVICE FIELD (RESERVED)
Bits 0 - 7
This register contains the detected received 8-bit value of the Service Field for the Header. This field is reserved for
the full protocol mode for future use and should be always a 00h.
CONFIGURATION REGISTER 45 ADDRESS (B4h) RX DATA LENGTH (HIGH)
Bits 0 - 7
This register contains the detected higher byte (bits 8-15) of the received Length Field contained in the Header. This
byte combined with the lower byte indicates the number of transmitted bits in the data packet.
CONFIGURATION REGISTER 46 ADDRESS (B8h) RX DATA LENGTH (LOW)
Bits 0 - 7
This register contains the detected lower byte of the received Length Field contained in the Header. This byte com-
bined with the upper byte indicates the number of transmitted bits in the data packet.
CONFIGURATION REGISTER 47 ADDRESS (BCh) RX CRC16 (HIGH)
Bits 0 - 7
This register contains the upper byte bits (8 -15) of the received CRC16 field Header. This register combined with the
lower byte represents a 16-bit CRC16 value protecting transmitted header. The fields protected are selected by con-
figuring the header control bits at configuration register 2.
CONFIGURATION REGISTER 48 ADDRESS (C0h) RX CRC16 (LOW)
Bits 0 - 7
This register contains the lower byte bits (0-7) of the received CRC16 field Header. This register combined with the
upper byte represents a 16-bit CRC16 value protecting transmitted header. The fields protected are selected by con-
figuring the header control bits at configuration register 2.
MSB
LSB
RX_CRC16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_CRC16(HIGH)
7 6 5 4 3
2 1 0
RX_CRC16(LOW)
7 6 5 4 3 2 1 0
NOTE: The receive CRC16 Field protects the following fields depending
upon the mode selection, as defined in configuration register 2.
Mode 0 CRC16 not used
Mode 1 CRC16 protects SFD
Mode 2 CRC16 protects SFD, and Length Field
Mode 3 CRC16 protects Signalling Field, Service Field, and Length Field
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