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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 101/140頁(yè) |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 55 of 131
6RW
Secondary Bus Reset
0
Do not force the assertion of the secondary interface RST#
1
Force the assertion of the secondary interface RST#
5RW
Master-Abort Mode
0
Do not report Master-Aborts (return x‘FFFF FFFF’ on reads and discard data on writes)
1
Report Master-Aborts by signaling Target-Abort if possible or by assertion of SERR# (if enabled)
If in PCI-X mode the bridge will return a Split Completion Message and it is up to the Host bridge to return
x‘FFFF FFFF’ data on any non-posted transaction when the non-posted transaction ends in Master Abort.
4RO
Reserved
0
Must return 0.
3RW
VGA Enable
0
Do not forward VGA compatible memory and I/O addresses from the primary to the secondary inter-
face unless they are enabled for forwarding by the defined I/O and memory address ranges.
1
Forward VGA compatible memory and I/O addresses from the primary interface to the secondary
interface (if the I/O Enable and Memory Enable bits are set) independent of the I/O and memory
address ranges and independent of the ISA Enable bit.
2RW
ISA Enable
0
Forward downstream all I/O addresses in address range defined by I/O Base and I/O Limit registers.
1
Forward upstream ISA I/O addresses in address range defined by I/O Base and I/O Limit registers in
the first 64 KB of PCI I/O address space (top 768 bytes of each 1 KB block).
1RW
SERR# Enable
0
Disable the forwarding of secondary SERR# to primary SERR#
1
Enable the forwarding of secondary SERR# to primary SERR#
0RW
Parity Error Response Enable
0
Ignore address and data parity errors on the secondary interface
1
Enable parity error detection and reporting on the secondary interface
Controls the response to address and data parity errors on the secondary interface. If this bit is set, the bridge
must take its normal action when a parity error is detected. If this bit is cleared, the bridge must ignore any par-
ity errors that it detects and continue normal operation. In either case, the parity error detected bit of the Sec-
ondary Status register gets set if an address or data parity error is detected.
Bit(s)
Access
Field Name and Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM21P100BGC | PCI BUS CONTROLLER, PBGA304 |
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
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| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
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