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| 型號(hào)： | IBM21P100BGB |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 11/140頁(yè) |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Signal Descriptions
Page 100 of 131
ppb11_signals.fm.03
July 9, 2001
7.4 Test Signals
S_PCIXCAP
I
1
Secondary Bus PCI-X Capable
Used in conjunction with the S_SEL100 signal to determine the operating frequency and
mode of the secondary interface.
S_PCIXCAP_PU
O
1
S_PCIXCAP Pull-up Driver
Part of a programmable pull-up circuit used to detect the three possible states of the
S_PCIXCAP input signal. A 1k
W resistor must be placed on the board and wired
between this signal and S_PCIXCAP.
S_SEL100
I
1
Secondary Bus 100MHz Indicator
Used to choose between 100MHz and 133MHz maximum operating frequency on the
secondary interface when in PCI-X mode. It has no meaning in PCI mode, but still
should be tied to a stable value.
0
133MHz
1
100MHz
Total
17
Table 15: List of Test Signals (Page 1 of 2)
Signal Name
I/O
Width
Description
JTG_TCK
I
1
JTAG Test Clock
Used to clock state information and test data into and out of the bridge during operation
of the IEEE 1149.1 Test Access Port (TAP). Internal Pull-up.
JTG_TDI
I
1
JTAG Test Data Input
Used to serially shift test data and test instructions into the bridge during TAP operation.
Internal Pull-up.
JTG_TDO
O
1
JTAG Test Output
Used to serially shift test data and test instructions out of the bridge during TAP opera-
tion.
JTG_TMS
I
1
JTAG Test Mode Select
Used to control the state of the TAP controller within the bridge. Internal Pull-up.
JTG_TRST#
I
1
JTAG Test Reset
Provides an asynchronous initialization of the TAP controller within the bridge. Internal
Pull-up.
T_DI1#
I
1
Driver Inhibit 1
Used to tri-state the outputs of non-test drivers during manufacturing test. It must be tied
high for normal system operation.
T_DI2#
I
1
Driver Inhibit 2
Used to tri-state the outputs of test drivers during manufacturing test. It must be tied high
for normal system operation.
Note: With the bridge containing internal pull-up resistors on TDI, TMS, TRST#, and TCK, system designers need to assure voltage
dividers are not generated by the possible implementation of pull-down resistors as defined in sections 4.3.3 and 4.4.1 of the PCI 2.2
specification.
Table 14: List of Strapping Pins and Other Signals (Page 2 of 2)
Signal Name
I/O
Width
Description
Note: Each strapping pin or reserved pin should have an unshared series resistor tying it to either ground or 3.3 V. The value of the
resistor may be selected to limit part number count, but the value should be greater than or equal to 100 Ohms and less than or equal to
5000 Ohms.
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