- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67681 > IBM21P100BGB PCI BUS CONTROLLER, PBGA304 PDF資料下載
參數(shù)資料
| 型號： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 137/140頁 |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁當(dāng)前第137頁第138頁第139頁第140頁
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Clocking and Reset
Page 88 of 131
ppb11_clock_reset.fm.03
July 9, 2001
6.3.1 Primary Interface
The primary interface is capable of operating in either conventional PCI mode or in PCI-X mode, at any of the
defined frequency ranges. Hence, when the IBM 133 PCI-X Bridge R1.1 is used on an add-in card, the
M66EN and PCIXCAP pins on the card edge connector should be left unconnected (except for a required
decoupling capacitor to provide an AC return path) to indicate this maximum capability. Should the add-in
card need to indicate a lesser capability, these signals should be pulled down or tied to ground appropriately
as defined by Section 6.2 of the
PCI-X Addendum to the PCI Local Bus Specification. Similarly, when the
bridge is used on a motherboard, the system designer should wire the M66EN and PCIXCAP signal networks
to all clients on the bus in the architected fashion to achieve the desired results.
The bridge does not have I/O pins for the M66EN or PCIXCAP signals on its primary interface. It adjusts its
internal configuration (including its internal PLL, if appropriate) solely on the basis of the initialization pattern it
detects on P_DEVSEL#, P_STOP#, and P_TRDY# at the rising edge of P_RST#. If the internal PLL is being
used (meaning that the bus is configured in PCI-X mode), a maximum of 100
ms from the rising edge of
P_RST# is required to lock the PLL to the frequency of the clock supplied on the P_CLK input.
6.3.2 Secondary Interface
The secondary interface is also capable of operating in either conventional PCI mode or in PCI-X mode, at
any of the defined frequency ranges. However, since the bridge acts as the central resource for the
secondary bus, it controls the mode and frequency determination process, which involves a number of steps.
As recommended by Section 14.2 of the
PCI-X Addendum to the PCI Local Bus Specification, the bridge
uses a programmable pull-up circuit to accomplish this task. A diagram of the circuit is shown in Figure 3 on
page 89. The figure also depicts the structure of the network connected to the S_PCIXCAP input of the
bridge. On the right hand side are examples of the types of connections that are expected when PCI-X 66,
PCI-X 133, and conventional PCI clients are attached to the bus (see the
PCI-X Addendum for details). There
are also two pull-up resistors on the net. The first is an external weak pull-up whose value of 56k
W is selected
to set the voltage of the S_PCIXCAP input below its low threshold when a PCI-X 66 client is attached. The
second is a strong pull-up, externally wired between the S_PCIXCAP and S_PCIXCAP_PU pins on the
module. Its value of 1k
W is selected to set the voltage of the S_PCIXCAP input above its high threshold when
all clients on the bus are only PCI-X 66 capable.
During the mode and frequency determination process, the S_PCIXCAP_PU driver is initially disabled, effec-
tively removing the strong pull-up resistor from the circuit. The bridge begins by sampling the value on its
S_PCIXCAP input. If it detects a b’0’ value, that means that one or more clients have either pulled the net to
ground (if they are PCI-X 66 capable) or tied it to ground (if they are only capable of conventional PCI opera-
tion). To distinguish between these two cases, the bridge then enables its S_PCIXCAP_PU driver to put the
strong pull-up into the circuit. If, after a sufficient time, its S_PCIXCAP input remains at a b’0’ value, the net
must be tied to ground by one or more clients; the bus therefore must be initialized to conventional PCI mode.
If the net can be pulled up, one or more clients are capable of only PCI-X 66 operation (and there are no
conventional PCI devices), so the bus is initialized to PCI-X 66 mode.
If the bridge initially samples a b’1’ value on its S_PCIXCAP input, that implies that all clients on the bus are
capable of PCI-X 133 operation. However, the initialization pattern must distinguish between the 66-100 MHz
and the 100-133 MHz clock frequency ranges. To do this, the bridge samples another input, S_SEL100, in
this case. If it detects a b’1’ value on the S_SEL100 input, the bus is initialized with the PCI-X 100 initialization
pattern. If the value is b’0’, the PCI-X 133 initialization pattern is used. These two ranges allow adjustment of
the clock frequency to account for bus loading conditions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM21P100BGC | PCI BUS CONTROLLER, PBGA304 |
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。