IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 48 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
5.2.4.19 Memory Base Register
The Memory Base register specifies the base of the memory mapped I/O address range bits 31:20 and is
used in conjunction with the Memory Limit register to specify a range of 32-bit addresses supported for
memory mapped I/O transactions on the PCI Bus. Address bits 19:0 are assumed to be x‘0 0000’ for the base
address.
5.2.4.20 Memory Limit Register
The Memory Limit register specifies the upper address of the memory-mapped I/O address range bits 31:20
and is used in conjunction with the Memory Base register to specify a range of 32-bit addresses supported for
memory mapped I/O transactions on the PCI Bus. Address bits 19:0 are assumed to be x‘F FFFF’ for the limit
address.
Address Offset
x‘20’
Access
See individual fields
Reset Value
x‘XXX0’
Non-prefetchable Memory Base Address
Reserved
15 14 13 12 11 10
9
876543210
Bit(s)
Access
Field Name and Description
15:4
RW
Non-prefetchable Memory Base Address
Address bits 31:20 of the base address for the address range of memory mapped I/O operations that are
passed from the primary to the secondary PCI bus.
3:0
RO
Reserved
Address Offset
Access
See individual fields
Reset Value
x‘XXX0’
Non-prefetchable Memory Limit Address
Reserved
15 14 13 12 11 10
9
876543210
Bit(s)
Access
Field Name and Description
15:4
RW
Non-prefetchable Memory Limit Address
Address bits 31:20 of the limit address for the address range of memory mapped I/O operations that are
passed from the primary to the secondary PCI bus.
3:0
RO
Reserved