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參數資料
| 型號： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁數： | 125/140頁 |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 77 of 131
5.2.5.20 PCI-X Bridge Status Register
The PCI-X Bridge Status register identifies the capabilities and current operating mode of the bridge on its
primary bus as listed in the following table.
Address Offset
x‘84’
Access
See individual bit descriptions. Reads to this register behave normally. Writes are
slightly different in that bits can be reset, but not set. A bit is reset whenever the
register is written, and the data in the corresponding bit location is a ‘1’.
Reset Value
x‘0003 00F8’
Res
e
rv
ed
Split
Reques
t
D
elayed
S
p
lit
Com
p
le
ti
on
Ov
errun
Unexpec
te
d
S
plit
Com
p
let
ion
Split
Com
p
le
ti
on
D
is
c
arded
133
MHz
C
apable
64-bit
D
ev
ic
e
Bus
N
um
ber
D
e
vi
ce
N
u
m
ber
F
unct
ion
Num
ber
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
98
76543210
Bit(s)
Access
Field Name and Description
31:22
RO
Reserved
21
RW
Split Request Delayed
This bit is set any time the bridge has a request to forward a transaction to the primary bus, but cannot because
there is not enough room within the limit specified in the Split Transaction Commitment Limit field in the
Upstream Split Transaction Control register. It is used by algorithms that optimize the setting of the upstream
Split Transaction Commitment Limit register.
0
the bridge has not delayed a Split Request.
1
the bridge has delayed a Split Request.
20
RW
Split Completion Overrun
This bit is set if the bridge terminates a Split Completion on the primary bus with Retry or Disconnect at Next
ADB because the bridge buffers are full. It is used by algorithms that optimize the setting of the upstream Split
Transaction Commitment Limit register.
0
the bridge has accepted all Split Completions
1
the bridge has terminated a Split Completion with Retry or Disconnect at Next ADB because the
bridge buffers were full.
19
RW
Unexpected Split Completion
This bit is set if an unexpected Split Completion with a Requester ID equal to the bridge’s primary bus number,
device number, and function number is received on the bridge’s primary interface.
0
no unexpected Split Completion has been received
1
an unexpected Split Completion has been received
18
RW
Split Completion Discarded
This bit is set if the bridge discards a Split Completion moving toward the primary bus because the requester
would not accept it.
0
no Split Completion has been discarded
1
a Split Completion has been discarded
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