參數(shù)資料
型號： IBM21P100BGB
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁數(shù)： 105/140頁
文件大小： 2032K
代理商： IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 59 of 131
11
RW
Enable Relaxed Ordering
This bit enables read completions that occur after the first read completion, for a read operation, to bypass
posted writes and complete with higher priority. Only read completions being presented on the primary inter-
face are affected by this bit.
0
Conventional mode, read command relaxed ordering disabled: each target bus read completion
transaction will be ordered with posted writes in the opposite direction(traveling the same direction
as the completion data). see PCI Bridge Specification 1.1, Table 5-2.
1
Conventional mode, read command relaxed ordering enabled: only the first read completion of a
read transaction will be required to meet the PCI ordering requirement for delayed read completion
vs posted writes (PCI Bridge Specification 1.1, Table 5-2) all subsequent read completions for the
same master transaction will be allowed to pass posted writes in the opposite direction.
This bit is used only for requests issued in PCI mode. For requests issued in PCI-X mode the relaxed order-
ing bit in the attribute field takes precedence.
10
RW
Secondary Special Delayed Read Mode Enable bit
Allows a secondary master to change memory read command (MR, MRL, or MRM) code after it has received
retry to another memory read command (MR, MRL, or MRM) code.
0
Retry any secondary master which repeats its transaction with command code changes
1
Completed MR, MRL, or MRM transaction on the secondary bus and the initiator (or another) mas-
ter on the secondary bus initiates a MR, MRL, or MRM transaction with the same address and BEs,
then the bridge will complete it normally.
This bit is ignored when the secondary interface is in PCI-X mode.
9:8
RW
Secondary Read prefetch mode bits
Controls prefetching for Memory Read transactions, that are initiated on the secondary bus.
00
One cache line prefetch
01
Reserved
10
Full prefetch
11
No prefetching, full handshake between initiator and target. Disconnect on first DWord.
These bits are ignored when the secondary interface is in PCI-X mode.
7:6
RW
Secondary Read Line prefetch mode bits
Controls prefetching for Memory Read Line transactions, that are initiated on the secondary bus.
00
One cache line prefetch
01
Reserved
10
Full prefetch
11
Reserved
These bits are ignored when the secondary interface is in PCI-X mode.
5:4
RW
Secondary Read Multiple prefetch mode bits
Controls prefetching for Memory Read Multiple transactions that are initiated on the secondary bus.
00
One cache line prefetch
01
Reserved
10
Full prefetch
11
Reserved
These bits are ignored when the secondary interface is in PCI-X mode.
3:0
RO
Reserved
Bit(s)
Access
Field Name and Description
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