- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67681 > IBM21P100BGB PCI BUS CONTROLLER, PBGA304 PDF資料下載
參數(shù)資料
| 型號： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 140/140頁 |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁當前第140頁
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_clock_reset.fm.03
July 9, 2001
Clocking and Reset
Page 91 of 131
Note that the values on these inputs are only valid at reset time; they may not be used to change the driver
mode dynamically, though they may be set differently at each reset if desired, to account for changes in bus
loading and mode. Regardless of the driver impedance used, signal analysis should always be done with the
actual or expected bus topology and wiring to verify proper operation. Nets may need to be tuned and series
terminations or other adjustments may be required in order to meet frequency targets.
6.6 Reset Functions and Operations
Each bus interface has an asynchronous bus reset signal that is used at power-on and other times to place
the IBM 133 PCI-X Bridge R1.1 into a known state. On the primary interface, the reset signal is an input to the
bridge; on the secondary interface, the reset signal is an output driven by the bridge in its role as the central
resource for that bus.
For the following discussions, please refer to Figure 4 and Table 11 on page 92.
6.6.1 Primary Reset
The bus reset for the primary interface is called P_RST#. It is an input to the bridge and is controlled by some
upstream central resource. When asserted, it forces all bus output signals from the bridge into their benign
states and sets all configuration registers within the bridge to their reset values as defined in
Transactions on page 20. Additionally, activating the P_RST# signal also causes the secondary bus reset
signal to be asserted, as required by the PCI / PCI-X specifications.
On the de-assertion or rising edge of the P_RST# signal, the initialization pattern is received off of the bus
and latched into the bridge. If the indication is that the primary bus is operating in PCI-X mode, an internal
PLL is used to source the clock tree for the primary clock domain. The appropriate range and tuning bits for
the PLL are set according to the indicated frequency range, and an internal PLL reset signal is deactivated to
allow the PLL to begin locking to the P_CLK input frequency. Since the PLL requires an allowance of 100
ms
to accomplish this frequency lock, an internal reset is held on the logic in the primary clock domain until this
time period has elapsed. While the internal logic reset is active, the bridge will not respond to any primary bus
transactions. When the primary bus is operating in PCI mode, the internal PLL for the primary interface is not
used. In this case, the internal PLL reset remains activated, keeping the PLL in bypass mode, and the internal
logic reset is held for only seven additional primary clock cycles after the rising edge of P_RST#.
6.6.2 Secondary Reset
The bus reset for the secondary interface is called S_RST# and it is an output from the bridge. Whenever
P_RST# is asserted or when the Secondary Bus Reset bit (bit 6) of the Bridge Control register is set to b’1’,
S_RST# is asserted immediately, asychronously to the secondary bus clock. When the Secondary Bus Reset
bit is being used to control S_RST#, the software must be sure that the required minimum Reset Active Time
(Trst)of 1 ms is met.
As alluded to in previous sections, a number of things must occur at or prior to the de-assertion of the
secondary bus reset signal. Once P_RST# is de-asserted or the Secondary Bus Reset bit is changed from
b’1’ to b’0’, indicating that S_RST# should be deactivated, the bridge will wait for the S_CLK_STABLE signal
to be asserted before proceeding. As stated previously, the S_CLK input must be stable at a frequency within
the bus capability limits prior to the assertion of S_CLK_STABLE. Since the
PCI Local Bus Specification
requires that the bus clock be stable for at least 100
ms prior to the de-assertion of the bus reset,
S_CLK_STABLE serves as a gate to a timer that ensures that this requirement is met. During this time delay
period, the determination of the secondary bus mode and frequency capability is made through the use of the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM21P100BGC | PCI BUS CONTROLLER, PBGA304 |
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。