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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 67/140頁(yè) |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Bus Operation
Page 24 of 131
ppb11_operations.fm.03
July 9, 2001
The bridge also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to
allow for the generation of upstream special cycle transactions, as explained below. All upstream Type 1
configuration read transactions are ignored by the bridge.
The bridge forwards Type 1 to Type 1 configuration read and configuration write transactions as delayed
transactions in PCI mode and as split transactions in PCI-X mode.
3.4.4 Special Cycle Generation by Bridge
The Type 1 configuration transaction format may be used to generate special cycle transactions in hierar-
chical PCI/PCI-X systems. Special cycle transactions can be generated from Type 1 configuration write trans-
actions in either the upstream or the downstream direction.
The bridge initiates a special cycle on the destination bus when a Type 1 configuration write transaction is
detected on the initiating bus and the following conditions are met during the address phase:
The command is a configuration write;
Address bits AD(1:0) are b‘01’;
The device number in address bits AD(15:11) is equal to b‘11111’;
The function number in address bits AD(10:8) is equal to b‘111’;
The register number in address bits AD(7:2) is equal to b‘000000’;and
The specified bus number is the same as the value in the bridge’s Secondary Bus Number register (for
downstream transactions) or matches the value in its Primary Bus Number register (for upstream transac-
tions).
When the bridge initiates the transaction on the destination interface, the command is changed from configu-
ration write to special cycle. Devices that use special cycles ignore the address and decode only the bus
command. The data phase contains the special cycle message. The transaction is forwarded as a delayed
transaction in PCI mode and as a split transaction in PCI-X mode. Once the transaction is completed on the
destination bus through the detection of the master abort condition, the bridge completes the transaction on
the originating bus by accepting the retry of the delayed command in PCI mode or by generating a completion
message in PCI-X mode.
Special cycle transactions received by the bridge as a target are ignored.
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