參數(shù)資料
型號： IBM21P100BGB
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁數(shù)： 48/140頁
文件大小： 2032K
代理商： IBM21P100BGB
ppb11_intro.fm.03
July 9, 2001
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
General Information
Page 7 of 131
2. General Information
2.1 Features
PCI-X Interfaces
Complies with
December 18, 1998; and PCI-X Addendum to the
PCI Local Bus specification, Revision 1.0a, July
24, 2000.
Uses the 3.3 V signaling environment and does not
support the optional 5 V I/O signaling levels.
Primary and secondary interface clocks may be
run synchronously or asynchronously
Concurrent primary and secondary bus operations
Supports configurations of PCI mode or PCI-X
mode on either bus in any combination
Memory Buffer Architecture
4KB of buffering for upstream memory burst read
commands, with up to eight active transactions
allowed
4KB of buffering for downstream memory burst read
commands, with up to eight active transactions
allowed
1KB of buffering for upstream posted memory write
commands, with up to eight active transactions
allowed
1KB of buffering for downstream posted memory
write commands, with up to eight active transactions
allowed
Allows one active single data phase (4-byte) delayed
or split transactionineachdirection
Power Management
Supports D0 and D3 power states
Transaction Forwarding
I/O, Memory, and Prefetchable Memory base and
limit registers for downstream forwarding
Inverse address decoding for upstream forwarding
Flat addressing model
Supports VGA-compatible addressing and palette
snooping for upstream transactions
Supports full 64-bit addressing and Dual Address
Cycles
Responds as medium-speed device on both inter-
faces
Configuration Registers
1 set of standard PCI and device specific configu-
ration registers, accessible from primary interface
Supports Type 0 and Type 1 configuration cycles
Optional Features
Capable of defining an optional opaque (unde-
coded) memory address region to facilitate appli-
cations with embedded processors
Supports secondary side PCI-X device privatiza-
tion
Bus Arbitration
On-chip programmable bus arbiter for the second-
ary bus with support for up to six external masters
Priority and masking control for each agent
IEEE 1149.1 JTAG port
Performs boundary-scan testing
2.2 Description
The IBM 133 PCI-X Bridge R1.1 transparently
connects two electrically separate PCI-X bus domains,
allowing concurrent operations on both buses. This
results in good utilization of the buses in various
system configurations and enables hierarchical expan-
sion of I/O bus structures.
As described by the PCI-X architecture, the IBM 133
PCI-X Bridge R1.1 is capable of handling 64-bit data at
a maximum bus frequency of 133 MHz (depending the
bus topology and load) and is backward compatible
with all 3.3V I/O conventional PCI interfaces.
The IBM 133 PCI-X Bridge R1.1 also provides exten-
sive buffering and prefetching mechanisms for efficient
transfer of data through the device, facilitating multi-
threaded operation and high system throughput.
.
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