參數(shù)資料
型號(hào): IBM21P100BGB
元件分類(lèi): 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁(yè)數(shù): 91/140頁(yè)
文件大小: 2032K
代理商: IBM21P100BGB
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)當(dāng)前第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 46 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
5.2.4.18 Secondary Status Register
This register is similar in function and bit definition to the Status register. However, its bits reflect status condi-
tions of the secondary interface.
Address Offset
x‘1E’
Access
See individual bit fields. Writes are slightly different in that bits can be reset, but
not set. A bit is reset whenever the register is written, and the data in the corre-
sponding bit location is a ‘1’.
Reset Value
x‘02A0’ in PCI mode, x‘0220’ in PCI-X mode
D
e
te
cted
Pa
ri
ty
Er
ror
Rec
e
iv
e
d
S
E
RR#
Receive
d
M
a
st
er
A
bort
Receive
d
T
a
rget
A
bort
Signaled
T
a
rget
Abort
DE
V
S
E
L
#
T
iming
Mas
ter
Dat
a
P
a
rit
y
E
rror
F
a
st
Bac
k
-t
o-B
a
ck
Capable
Res
e
rv
ed
66
M
H
z
C
apable
Reserved
15 14 13 12 11 10
9
876543210
Bit(s)
Access
Field Name and Description
15
RW
Detected Parity Error Status
0
Device did not detect a parity error
1
Device detected a parity error
14
RW
Signaled System Error Status
0
Device did not receive a SERR# signal on the secondary interface
1
Device received a SERR# signal on the secondary interface
13
RW
Received Master Abort Status
0
Bus master transaction was not terminated with bus Master Abort
1
Bus master transaction terminated with bus Master Abort
12
RW
Received Target Abort Status
0
Bus master transaction was not terminated by Target Abort
1
Bus master transaction terminated by Target Abort
11
RW
Signaled Target Abort Status
0
Target device did not terminate a transaction with Target Abort
1
Target device terminated a transaction with Target Abort
10:9
RO
Device Select (DEVSEL#) Timing Status
01
Medium
8RW
Data Parity Status
0
No data parity errors encountered
1
Data parity errors encountered (this bit for Bus Masters only)
7RO
Fast Back-to-Back Capable
0
Target not capable of accepting fast back-to-back transactions in PCI-X mode
1
Target capable of accepting fast back-to-back transactions in conventional mode
This bit is set to a b‘1’ by hardware when the secondary interface is in PCI mode and is set to a b‘0’ when the
secondary interface is in PCI-X mode.
相關(guān)PDF資料
PDF描述
IBM21P100BGC PCI BUS CONTROLLER, PBGA304
IBM25403GCX-3JC76C2 RISC PROCESSOR, PQFP16
IBM25405GP-3BA200C2 RISC PROCESSOR, PBGA456
IBM25EMPPC603EFG-100 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240
IBM25EMPPC603EBG-100 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM24L5086 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述:
IBM25403GCX-3BC80C2 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA
IBM25403GCX-3JC50C2 制造商:IBM 功能描述:403GCX-3JC50C2
IBM25403GCX-3JC66C2 制造商:IBM 功能描述:
IBM25403GCX3JC76C2 制造商:IBM 功能描述: