
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 46 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
5.2.4.18 Secondary Status Register
This register is similar in function and bit definition to the Status register. However, its bits reflect status condi-
tions of the secondary interface.
Address Offset
x‘1E’
Access
See individual bit fields. Writes are slightly different in that bits can be reset, but
not set. A bit is reset whenever the register is written, and the data in the corre-
sponding bit location is a ‘1’.
Reset Value
x‘02A0’ in PCI mode, x‘0220’ in PCI-X mode
D
e
te
cted
Pa
ri
ty
Er
ror
Rec
e
iv
e
d
S
E
RR#
Receive
d
M
a
st
er
A
bort
Receive
d
T
a
rget
A
bort
Signaled
T
a
rget
Abort
DE
V
S
E
L
#
T
iming
Mas
ter
Dat
a
P
a
rit
y
E
rror
F
a
st
Bac
k
-t
o-B
a
ck
Capable
Res
e
rv
ed
66
M
H
z
C
apable
Reserved
15 14 13 12 11 10
9
876543210
Bit(s)
Access
Field Name and Description
15
RW
Detected Parity Error Status
0
Device did not detect a parity error
1
Device detected a parity error
14
RW
Signaled System Error Status
0
Device did not receive a SERR# signal on the secondary interface
1
Device received a SERR# signal on the secondary interface
13
RW
Received Master Abort Status
0
Bus master transaction was not terminated with bus Master Abort
1
Bus master transaction terminated with bus Master Abort
12
RW
Received Target Abort Status
0
Bus master transaction was not terminated by Target Abort
1
Bus master transaction terminated by Target Abort
11
RW
Signaled Target Abort Status
0
Target device did not terminate a transaction with Target Abort
1
Target device terminated a transaction with Target Abort
10:9
RO
Device Select (DEVSEL#) Timing Status
01
Medium
8RW
Data Parity Status
0
No data parity errors encountered
1
Data parity errors encountered (this bit for Bus Masters only)
7RO
Fast Back-to-Back Capable
0
Target not capable of accepting fast back-to-back transactions in PCI-X mode
1
Target capable of accepting fast back-to-back transactions in conventional mode
This bit is set to a b‘1’ by hardware when the secondary interface is in PCI mode and is set to a b‘0’ when the
secondary interface is in PCI-X mode.